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w WM8310 processor power management subsystem wolfson microelectronics plc to receive regular email updates, sign up at http://www.wolfsonmicro.com/ enews pre-production, may 2012, rev 3.1 copyright ? 2012 wolfson microelectronics plc description the WM8310 is an integrated power-management subsystem which provides a cost-effective, flexible, single-chip solution for power management. it is specifically targeted at the requirements of a range of low-power portable consumer products, but is suitable to any application with a multimedia processor. the WM8310 is designed to operate as a system pmic supporting a variety of industry-standard processors and accessories in a wide range of consumer multimedia applications. the start-up behaviour and configur ation is fully programmable in an integrated otp non-volatile memory. this highly flexible solution helps reduce time-to- market, as changing application requirements can be very easily accommodated in the otp. the instantconfig? interface enables an external eeprom to configure the WM8310. the WM8310 power management subsystem comprises of four programmable dc-dc conver ters, eleven ldo regulators (four of which are low-noise for supplying sensitive analogue subsystems). the integrated ot p bootstrap circuitry controls the start-up sequencing and volt ages of the converters and regulators as well as the sequencing of system clocks. WM8310 can be powered from a battery, a wall adaptor or from a usb power source. an on-chip regulator provides power for always-on pmic functions such as register map and the rtc. the device provi des autonomous backup battery switchover. a low-power ldo is included to support ?alive? processor power domains external to the WM8310. a linear on-chip battery charger supports trickle charging and constant current / constant voltage charging of single-cell lithium-ion / lithium-polymer batteries. the charge current, termination voltage, and charger time-out are programmable. WM8310 detects and handles battery fault conditions with a minimum of system software involvement. a 12-bit auxiliary adc supports a wide range of applications for internal as well as external analogue sampling, such as voltage detection and temperature measurement. WM8310 includes a crystal oscillator, an internal rc oscillator and frequency locked loop (fll) to generate clock signals for autonomous system start-up and processor clocking. a secure real-time clock (s-rtc) and alarm function is included, capable of system wake-up from low-power modes. a watchdog function is provided to ensure system integrity. to maximise battery life, highly-granular power management enables each function in the WM8310 subsystem to be independently powered down through a control interface or alternatively through register and otp-configurable gpios. the device offers a standby pow er consumption of <10ua, making it particularly suitable for portable applications. the WM8310 is supplied in a 7x7mm 169-ball bga package, ideal for use in portable systems. the WM8310 forms part of the wolfson series of audio and power management solutions. features power management ? 2 x dc-dc synchronous buck converters (0.6v - 1.8v, 1.2a, dvs) ? 1 x dc-dc synchronous buck converter (0.85v - 3.4v, 1a) ? 1 x dc-dc boost converter (up to 30v, up to 90ma) ? 1 x ldo regulator (0.9v - 3.3v, 300ma, 1 ? ) ? 2 x ldo regulators (0.9v - 3.3v, 200ma, 1 ? ) ? 3 x ldo regulators (0.9v - 3.3v, 100ma, 2 ? ) ? 2 x low-noise ldo regulators (1.0v - 3.5v, 200ma, 1 ? ) ? 2 x low-noise ldo regulators (1.0v - 3.5v, 150ma, 2 ? ) ? 1 x ?alive? ldo regulator (0.8v ? 1.55v, up to 25ma) backlight led current sinks ? 2 x programmable constant current sinks, suitable for multi-led display backlight control battery charger ? programmable single-cell lithium-ion / lithium-polymer battery charger (1a max charge current) ? battery monitoring for temperature and voltage ? autonomous backup battery charging and switching system control ? i 2 c or spi compatible primary control interface ? interrupt based feedback communication scheme ? watchdog timer and system reset control ? autonomous power sequenc ing and fault detection ? intelligent power path and power source selection ? otp memory bootstrap configuration function additional features ? auxiliary adc for multi-function analogue measurement ? 128-bit pseudo-random unique id ? secure real-time clock with wake-up alarm ? 12 x configurable multi- function (gpio) pins ? comprehensive clocking scheme: low-power 32khz rtc crystal oscillator, frequency locked loop, gpio clock output and 4mhz rc clock for power management ? system led outputs indicating power state, battery charger or fault status ? selectable usb current limiting up to 1.8a (in accordance with usb battery charging specification rev 1.1) package options ? 7x7mm, 169-ball bga package, 0.5mm ball pitch applications ? portable media players ? portable navigation devices ? cellular handsets ? electronic books ? electronic gaming devices
WM8310 pre-production w pp, may 2012, rev 3.1 2 block diagram ` dc1gnd dc1fb dc1lx dc1vdd dc-dc1 buck 0.6 to 1.8v 1.2a ldo2vout ldo1vdd ldo 2 standard ldo 0.9 to 3.3v 200ma ldo 1 standard ldo 0.9 to 3.3v 300ma ldo4vout ldo3vdd ldo5vdd dc2gnd dc2fb dc2lx dc2vdd dc-dc2 buck 0.6 to 1.8v 1.2a dc4gnd dc4fb dc4lx dc4vdd dc-dc4 boost up to 30v, up to 90ma ldo 3 standard ldo 0.9 to 3.3v 200ma ldo 4 standard ldo 0.9 to 3.3v 100ma ldo 5 standard ldo 0.9 to 3.3v 100ma WM8310 irq sda2 sclk2 sda1 sclk1 sdout1 cs reset dbvdd dbgnd dvs dc3gnd dc3fb dc3lx dc3vdd dc-dc3 buck 0.85 to 3.4v 1a ldo1vout ldo2vdd ldo3vout ldo4vdd ldo5vout ldo 7 analogue ldo 1.0 to 3.5v 200ma ldo7vout ldo7vdd dvs xto xti clkout real-time clock wake-up timer 32.768khz oscillator fll clkin cifmode gpio6 gpio3 gpio4 gpio5 gpio1 gpio2 gpio10 gpio7 gpio8 gpio9 instant- config? eeprom interface otp nvm bootstrap config & unique id primary control interface multi- function pin (gpio) controller ap interface, gpios and pm control power management control 1 to 4mhz rc oscillator register map and application processor interface pm sub- system monitoring on interrupt and reset controller gpio12 gpio11 system status led driver led1 led2 ldo 11 alive ldo 0.8 to 1.55v 25ma ldo 12 internal ldo 2.1v 2ma ldo11vout ldo12vout (backup battery connection) ldo13vout ldo 13 internal ldo 2.5v 20ma progvdd aux adc ntcbias ntcmon usbvmon sysvmon battvmon auxadcin3 auxadcin4 auxadcin1 auxadcin2 supply voltage and battery monitor wallvdd xoscgnd led sink isink1 isink2 isinkgnd gnd pvdd auxiliary functions power management ldo6vout ldo 6 standard ldo 0.9 to 3.3v 100ma ldo6vdd ldo8vout ldo9vdd ldo 8 analogue ldo 1.0 to 3.5v 200ma ldo 10 analogue ldo 1.0 to 3.5v 150ma ldo 9 analogue ldo 1.0 to 3.5v 150ma ldo8vdd ldo9vout ldo10vdd ldo10vout battery charger 1a vrefc irefr usbvdd sysvdd battvdd references wallvdd wallfetena battfetena power path management switching matrix refgnd
pre-production WM8310 w pp, may 2012, rev 3.1 3 typical applications the WM8310 is designed as a system pmic device t hat manages multiple power supply paths (wall adapter, usb, battery) and generates configurable dc supplies to power processors and associated peripherals within a system. the WM8310 provi des three dc-dc synchronous buck (step-down) converters and one dc-dc boost (st ep-up) converter. eleven ldo regulators provide a high degree of flexibility to provide power to multiple dev ices, with the capability to power-up and power-down different circuits independently. two of the dc-dc buck converters incorporate wolfson?s buckwise? technology specifically designed to handle rapid changes in l oad current; programmable slew rate dvs is also provided, as required by modern application processors. se lectable operating modes on all of the dc-dc converters allow each converter to be optimally configured for light, heavy or transient load conditions. flexible operating conf igurations allow the converters to be tailored for minimum pcb area, maximum performance, or for maximum e fficiency. the analogue ldos provide low-noise outputs suitable for powering sensit ive circuits such as rf / wi -fi / bluetooth radio applications. the WM8310 powers up the converters and ldos according to a programmable sequence. a configurable ?sleep? state is also available, providing support for an al ternate configuration, typically for low-power / standby operation. the power c ontrol sequences and many other parameters can be stored in an integrated user-configurable otp (o ne-time programmable) memory or may be loaded from an external memory. the WM8310 supports t he programming and verification of the integrated otp memory. the WM8310 provides power path management whic h seamlessly switches between wall adapter, usb and battery power sources according to the prev ailing conditions. a backup power source is also supported in order to maintain the real time clo ck (rtc) in the absence of any other supplies. the WM8310 provides a configurable batte ry charger for the main battery, powered from either the wall adapter or usb supplies. the backup power source is maintained using a constant-voltage output from the WM8310. programmable gpio pins may be configured as hardware inputs fo r general use or for selecting different power management configurations. as output s, the gpios can provide indications of the device status, or may be used as control signal s for other power management circuits. the WM8310 also provides two led drivers, wh ich can be controlled manually or conf igured as status indicators for the otp memory programmer, operating power state or battery charger.
WM8310 pre-production w pp, may 2012, rev 3.1 4 table of contents descript ion ....................................................................................................... 1 ? featur es ............................................................................................................ 1 ? applications ..................................................................................................... 1 ? block diag ram ................................................................................................ 2 ? typical appl ication s .................................................................................... 3 ? table of co ntents ......................................................................................... 4 ? 1 ? pin configuration .................................................................................. 8 ? 2 ? ordering info rmation ......................................................................... 8 ? 3 ? pin descri ption ....................................................................................... 9 ? 4 ? thermal character istics ................................................................ 13 ? 5 ? absolute maximu m ratin gs.............................................................. 14 ? 6 ? recommended operatin g condit ions .......................................... 14 ? 7 ? electrical charact eristics ........................................................... 15 ? 7.1 ? dc-dc synchronous buck converters ............................................... 15 ? 7.2 ? dc-dc step up co nverter ......................................................................... 17 ? 7.3 ? current sinks ................................................................................................ 17 ? 7.4 ? ldo regulators ............................................................................................ 18 ? 7.5 ? reset thresholds ....................................................................................... 22 ? 7.6 ? references .................................................................................................... 22 ? 7.7 ? battery charger ......................................................................................... 23 ? 7.8 ? usb power control .................................................................................... 24 ? 7.9 ? general purpose inputs / outputs (gpio) ........................................... 24 ? 7.10 ? digital interfaces .................................................................................... 25 ? 7.11 ? auxiliary adc .............................................................................................. 25 ? 7.12 ? system status led drivers ................................................................... 25 ? 7.13 ? clocking ....................................................................................................... 25 ? 8 ? typical power co nsumption ........................................................... 26 ? 9 ? typical performance data .............................................................. 27 ? 9.1 ? dc-dc converters ....................................................................................... 27 ? 9.2 ? ldo regulators ............................................................................................ 27 ? 10 ? signal timing re quiremen ts ............................................................ 28 ? 10.1 ? control interface ................................................................................... 28 ? 11 ? device des cription .............................................................................. 30 ? 11.1 ? general description ............................................................................... 30 ? 11.2 ? power states ............................................................................................. 30 ? 11.3 ? power state control ............................................................................. 32 ? 11.4 ? power state interrupts ........................................................................ 37 ? 11.5 ? power state gpio indication ................................................................ 37 ? 11.6 ? on pin function .......................................................................................... 38 ? 11.7 ? reset pin function ................................................................................... 39 ? 12 ? control interface .............................................................................. 41 ? 12.1 ? general description ............................................................................... 41 ? 12.2 ? 2-wire (i2c) co ntrol mode ...................................................................... 41 ? 12.3 ? 4-wire (spi) co ntrol mode ...................................................................... 44 ? 12.4 ? register locking ...................................................................................... 44 ? 12.5 ? software reset a nd chip id .................................................................. 45 ? 12.6 ? software scratch register ................................................................ 45 ?
pre-production WM8310 w pp, may 2012, rev 3.1 5 13 ? clocking and oscilla tor cont rol .............................................. 46 ? 13.1 ? general description ............................................................................... 46 ? 13.2 ? crystal oscillator ................................................................................. 48 ? 13.3 ? frequency locked loop (fll) ............................................................... 49 ? 13.3.1 ? fll auto mode ................................................................................................................ 53 ? 14 ? instantconfig? (ice) and ot p memory co ntrol ...................... 54 ? 14.1 ? general description ............................................................................... 54 ? 14.2 ? ice and otp memory definition ............................................................ 54 ? 14.3 ? bootstrap (start-up) function ........................................................... 55 ? 14.3.1 ? start-up from otp memo ry ...................................................................................... 55 ? 14.3.2 ? start-up from ice memory (development mode) .............................................. 56 ? 14.3.3 ? start-up from dcrw register se ttings ............................................................. 56 ? 14.3.4 ? external ice memory connect ion ......................................................................... 56 ? 14.4 ? otp / ice memory control ...................................................................... 57 ? 14.4.1 ? entering / exiting th e program state ................................................................. 58 ? 14.4.2 ? otp / ice read comma nd .............................................................................................. 58 ? 14.4.3 ? otp write command ..................................................................................................... 59 ? 14.4.4 ? otp verify command .................................................................................................... 59 ? 14.4.5 ? otp finalise command ................................................................................................. 60 ? 14.4.6 ? otp control registe r ................................................................................................ 61 ? 14.5 ? otp / ice interrupts ................................................................................. 62 ? 14.6 ? dcrw memory co ntents ......................................................................... 62 ? 14.6.1 ? dcrw pag e 0 ................................................................................................................... . 63 ? 14.6.2 ? dcrw pag e 1 ................................................................................................................... . 63 ? 14.6.3 ? dcrw pag e 2 ................................................................................................................... . 63 ? 14.6.4 ? dcrw pag e 3 ................................................................................................................... . 65 ? 14.6.5 ? dcrw pag e 4 ................................................................................................................... . 66 ? 15 ? power manag ement ............................................................................ 67 ? 15.1 ? general description ............................................................................... 67 ? 15.2 ? dc-dc converter and ldo regulator control ............................ 67 ? 15.3 ? timeslot control and hardware enable (gpio) control ......... 68 ? 15.4 ? operating mode control ...................................................................... 69 ? 15.4.1 ? dc-dc synchronous buck converte rs ................................................................ 69 ? 15.4.2 ? dc-dc boost con verters .......................................................................................... 69 ? 15.4.3 ? ldo regula tors ............................................................................................................ 69 ? 15.5 ? output voltage control ...................................................................... 70 ? 15.5.1 ? dc-dc synchronous buck converte rs ................................................................ 70 ? 15.5.2 ? dc-dc boost con verters .......................................................................................... 70 ? 15.5.3 ? ldo regulato rs 1- 10 .................................................................................................... 70 ? 15.5.4 ? ldo regula tor 11 .......................................................................................................... 70 ? 15.6 ? dc-dc synchronous buck co nverter control ............................ 71 ? 15.7 ? dc-dc boost conver ter control....................................................... 72 ? 15.8 ? ldo regulator control ........................................................................ 72 ? 15.9 ? hardware contro l (gpio) ...................................................................... 72 ? 15.10 ? fault protection ...................................................................................... 73 ? 15.11 ? monitoring and fa ult reporting ....................................................... 74 ? 15.12 ? power management regi ster definitions ...................................... 74 ? 15.12.1 ? dc-dc converter and ldo regulator enable ................................................... 74 ? 15.12.2 ? dc-dc synchronous buck co nverter co ntrol ................................................ 75 ? 15.12.3 ? dc-dc boost conver ter cont rol .......................................................................... 80 ? 15.12.4 ? ldo regulator contro l ............................................................................................ 81 ? 15.12.5 ? external power enable (epe) cont rol ................................................................ 89 ? 15.12.6 ? monitoring and fa ult report ing ........................................................................... 89 ? 15.13 ? power management interrupts ......................................................... 90 ?
WM8310 pre-production w pp, may 2012, rev 3.1 6 15.14 ? power good indi cation .......................................................................... 91 ? 15.15 ? dc-dc converter operation ................................................................ 92 ? 15.15.1 ? overview ...................................................................................................................... .... 92 ? 15.15.2 ? dc-dc synchronous buck converte rs ................................................................ 93 ? 15.15.3 ? dc-dc step up co nverte r .......................................................................................... 96 ? 15.16 ? ldo regulator operation ..................................................................... 97 ? 15.16.1 ? overview ...................................................................................................................... .... 97 ? 15.16.2 ? ldo regula tors ............................................................................................................ 97 ? 16 ? current si nks ....................................................................................... 99 ? 16.1 ? general description ............................................................................... 99 ? 16.2 ? current sink control ............................................................................ 99 ? 16.2.1 ? enabling the si nk current ....................................................................................... 99 ? 16.2.2 ? programming the sink curre nt ........................................................................... 100 ? 16.2.3 ? on/off ramp timing ..................................................................................................... 101 ? 16.3 ? current sink interrupts ..................................................................... 102 ? 16.4 ? led driver conne ctions ....................................................................... 103 ? 17 ? power supply contro l ................................................................... 104 ? 17.1 ? general description ............................................................................. 104 ? 17.2 ? battery powered operation ............................................................. 106 ? 17.3 ? wall adaptor powere d operation .................................................. 106 ? 17.4 ? usb powered o peration ....................................................................... 107 ? 17.5 ? power path manageme nt interrupts ............................................. 108 ? 17.6 ? backup power .......................................................................................... 109 ? 17.7 ? battery charger .................................................................................... 109 ? 17.7.1 ? general des cription ................................................................................................. 109 ? 17.7.2 ? battery charger enabl e ......................................................................................... 111 ? 17.7.3 ? fast char ging .............................................................................................................. 11 2 ? 17.7.4 ? charger timeout a nd terminat ion ...................................................................... 113 ? 17.7.5 ? battery charge current monitori ng ................................................................ 115 ? 17.7.6 ? battery fault / overvo ltage condi tions ......................................................... 116 ? 17.7.7 ? battery temperature monitori ng ...................................................................... 116 ? 17.7.8 ? battery charger interrupts ................................................................................ 118 ? 17.7.9 ? battery charger status ......................................................................................... 119 ? 18 ? auxiliary adc ....................................................................................... 120 ? 18.1 ? general description ............................................................................. 120 ? 18.2 ? auxadc control ...................................................................................... 120 ? 18.3 ? auxadc readback .................................................................................... 122 ? 18.4 ? digital comparators ............................................................................. 123 ? 18.5 ? auxadc interrupts ................................................................................. 125 ? 19 ? reserved ............................................................................................... 125 ? 20 ? real-time clo ck (rtc ) ....................................................................... 126 ? 20.1 ? general description ............................................................................. 126 ? 20.2 ? rtc control .............................................................................................. 126 ? 20.3 ? rtc interrupts ........................................................................................ 128 ? 20.4 ? digital rights management ................................................................ 129 ? 20.5 ? backup mode clocki ng options ........................................................ 129 ? 21 ? general purpose inputs / outputs (g pio) ................................ 130 ? 21.1 ? general description ............................................................................. 130 ? 21.2 ? gpio functions ......................................................................................... 130 ? 21.3 ? configuring gp io pins ........................................................................... 132 ? 21.4 ? gpio interrupts ....................................................................................... 136 ? 22 ? system status led driver s ............................................................ 137 ?
pre-production WM8310 w pp, may 2012, rev 3.1 7 22.1? general description ............................................................................. 137 ? 22.2? led driver control ................................................................................ 137 ? 22.2.1 ? otp program status ................................................................................................. 137 ? 22.2.2 ? power state status .................................................................................................. 138 ? 22.2.3 ? charger st atus .......................................................................................................... 138 ? 22.2.4 ? led driver manua l mode .......................................................................................... 138 ? 22.3? led driver conne ctions ....................................................................... 140 ? 23 ? interrupt controller .................................................................... 141 ? 23.1? primary interrupts ............................................................................... 142 ? 23.2? secondary interrupts ......................................................................... 144 ? 23.2.1 ? power state interrupt ............................................................................................ 144 ? 23.2.2 ? thermal inte rrupts .................................................................................................. 145 ? 23.2.3 ? gpio interrup ts .......................................................................................................... 145 ? 23.2.4 ? on pin inte rrupts ....................................................................................................... 145 ? 23.2.5 ? watchdog inte rrupts .............................................................................................. 146 ? 23.2.6 ? reserved ........................................................................................................................ 146 ? 23.2.7 ? reserved ........................................................................................................................ 146 ? 23.2.8 ? auxadc inte rrupts .................................................................................................... 146 ? 23.2.9 ? power path manageme nt interrup ts ................................................................. 147 ? 23.2.10 ? current sink interrup ts......................................................................................... 147 ? 23.2.11 ? real time cloc k interrup ts ................................................................................... 148 ? 23.2.12 ? otp memory in terrupts ........................................................................................... 148 ? 23.2.13 ? reserved ........................................................................................................................ 149 ? 23.2.14 ? battery charger interrupts ................................................................................ 149 ? 23.2.15 ? high current in terrupts ........................................................................................ 150 ? 23.2.16 ? undervoltage in terrupts ...................................................................................... 151 ? 24 ? resets and supply voltage monitoring .................................. 152 ? 24.1? resets ......................................................................................................... 152 ? 24.2? hardware reset ...................................................................................... 154 ? 24.3? software reset ...................................................................................... 154 ? 24.4? supply voltage monitoring ............................................................... 156 ? 25 ? watchdog timer ................................................................................. 158 ? 26 ? temperature sensing ...................................................................... 160 ? 27 ? voltage and current referenc es ............................................. 161 ? 27.1? voltage reference (vref) ................................................................... 161 ? 27.2? current reference (iref) ................................................................... 161 ? 28 ? register map o verview ................................................................... 162 ? 29 ? register bits by addr ess ............................................................... 169 ? 30 ? applications in formation .............................................................. 277 ? 30.1? typical connections ............................................................................. 277 ? 30.2? voltage and current refe rence components .......................... 278 ? 30.3? dc-dc buck converter ex ternal components ........................... 278 ? 30.4? dc-dc (step-up) converter external components ................... 281 ? 30.5? ldo regulator externa l components .......................................... 283 ? 30.6? battery temperature monitoring components ........................ 284 ? 30.7? pcb layout ................................................................................................. 287 ? 31 ? package diag ram ............................................................................... 288 ? 32 ? important no tice ............................................................................... 289 ? 33 ? revision hi story ................................................................................. 290 ?
WM8310 pre-production w pp, may 2012, rev 3.1 8 1 pin configuration 12345678910111213 a ba ttfeten a_n pv dd1 dc3fb dc3v dd dc3lx dc3gnd dc2v dd dc2lx dc2gnd dc1gnd dc1lx dc1v dd dc1fb a b gnd gnd gnd dc3v dd dc3lx dc3gnd dc2v dd dc2lx dc2gnd dc1gnd dc1lx dc1v dd gnd b c ldo6v dd ldo6v out gnd gnd dc3gnd dc2fb gnd gnd gnd gnd gnd gnd irq_n c d ldo5v dd ldo5v out gnd progv dd sdout1 gnd sda 1 sclk1 dbv dd1 cs_n reset_n gnd gpio2 d e ldo4v dd ldo4v out gnd gnd gpio1 gpio3 gpio7 gpio8 dbvdd1 ldo13vou t dc4fb gnd gpio9 e f ldo10vdd ldo10vou t ldo9v out gnd gnd gnd gpio5 gpio6 gpio4 gnd gnd gnd dc4v dd f g ldo8v dd ldo9v dd ldo8v out gnd a uxa dcin4 gnd gnd gnd gnd gpio12 gpio11 dc4lx dc4gnd g h ldo7v dd ldo7v out dnc ntcbia s ntcmon v refc gnd sda 2 dnc dnc dnc gpio10 dbgnd h j ldo3vdd ldo3vout cifmode wallvdd sysvdd sysvdd usbvmon irefr auxadcin1 gnd led1 dbvdd3 dnc j k ldo2vdd ldo2vout dbgnd wa llfete na _n sy sv dd sy sv dd usbv dd ba ttv mon gnd gnd led2 dnc ldo11vou t k l ldo1v dd ldo1v out dbgnd clkout usbvdd ba ttvdd sysvdd gnd gnd xti isinkgnd isink2 refgnd l m gnd dnc dnc dbgnd usbv dd gnd gnd gnd sclk2 xto isinkgnd isink1 a uxa dcin2 m n dnc dnc dbv dd2 clkin sy sv mon sy sv dd ba ttv dd usbv dd pv dd2 ldo12vou t on_n xoscgnd auxadcin3 n 7x7 bga - top view (WM8310) 2 ordering information order code otp temperature range (t a ) package moisture sensitivity level peak soldering temperature WM8310cgeb/v unprogrammed -40 ? c to +85 ? c 169-ball (7 x 7mm) (pb-free) msl3 260 ? c WM8310cgeb/rv unprogrammed -40 ? c to +85 ? c 169-ball (7 x 7mm) (pb-free, tape and reel) msl3 260 ? c WM8310cgebxxx/rv* custom -40 ? c to +85 ? c 169-ball (7 x 7mm) (pb-free, tape and reel) ** msl3 260 ? c note: reel quantity = 2200 * xxx = unique otp part number * custom otp minimum order quantity 22,000
pre-production WM8310 w pp, may 2012, rev 3.1 9 3 pin description notes: 1. pins are sorted by functional groups. 2. the power domain associated with each pin is noted; vpm ic is the domain powered by ldo12 for the ?always-on? functions internal to the WM8310. 3. note that an external level-shifter may be requi red when interfacing between different power domains. pin name type power domain description auxiliary adc j7 usbvmon analogue input usbvdd usbvdd supply voltage monitor n5 sysvmon analogue input sysvdd sysvdd supply voltage monitor k8 battvmon analogue input battvdd battvdd supply voltage monitor j9 auxadcin1 analogue input/output sysvdd auxiliary analogue input 1 / battery charge current monitor output m13 auxadcin2 analogue input auxiliary analogue input 2 n13 auxadcin3 analogue input auxiliary analogue input 3 g5 auxadcin4 analogue input dbvdd auxiliary analogue input 4 clocking and real time clock m10 xto analogue output vpmic crystal drive output l10 xti analogue input crystal drive input or 32.768khz cmos clock input n12 xoscgnd supply crystal oscillator ground l4 clkout digital output dbvdd cmos clock output configurable open drain / cmos mode. (external 4.7k ? pull-up recommended in open drain mode.) n4 clkin digital input cmos fll clock input general purpose input / output e5 gpio1 digital i/o dbvdd or vpmic gpio pin 1 selectable pull-up/pull-down. d13 gpio2 digital i/o gpio pin 2 selectable pull-up/pull-down. e6 gpio3 digital i/o gpio pin 3 selectable pull-up/pull-down. f9 gpio4 digital i/o dbvdd or sysvdd gpio pin 4 selectable pull-up/pull-down. f7 gpio5 digital i/o gpio pin 5 selectable pull-up/pull-down. f8 gpio6 digital i/o gpio pin 6 selectable pull-up/pull-down. e7 gpio7 digital i/o dbvdd or vpmic gpio pin 7 selectable pull-up/pull-down. e8 gpio8 digital i/o gpio pin 8 selectable pull-up/pull-down. e13 gpio9 digital i/o gpio pin 9 selectable pull-up/pull-down. h12 gpio10 digital i/o dbvdd or sysvdd gpio pin 10 selectable pull-up/pull-down. g11 gpio11 digital i/o gpio pin 11 selectable pull-up/pull-down. g10 gpio12 digital i/o gpio pin 12 selectable pull-up/pull-down.
WM8310 pre-production w pp, may 2012, rev 3.1 10 pin name type power domain description processor interface and ic control n11 on digital input vpmic on request pin (internal pull-up) d11 reset digital i/o dbvdd system reset input and open drain output. (internal pull-up) c13 irq digital output dbvdd pmic interrupt flag output. configurable open drain / cmos mode. (internal pull-up in open drain mode.) j3 cifmode digital input dbvdd primary control interface mode select: 0 = i 2 c compatible control interface mode 1 = spi compatible control interface mode spi compatible control interface mode i 2 c compatible control interface mode d5 sdout1 digital output dbvdd control interface serial data out. open drain output; external 4.7k ? pull-up recommended. no function d8 sclk1 digital input control interface serial clock control interface serial clock d7 sda1 digital i/o control interface serial data in control interface serial data input and open drain output. external 4.7k ? pull-up recommended. (output can extend above dbvdd domain.) d10 cs digital input control interface chip select i 2 c address select: 0 = 68h 1 = 6ch m9 sclk2 digital i/o vpmic control interface serial clock for external instantconfig? eeprom (ice) (internal pull-down) h8 sda2 digital i/o control interface serial data to/from external instantconfig? eeprom (ice (internal pull-down) d9, e9 dbvdd1 supply digital buffer supply n3 dbvdd2 supply digital buffer supply j12 dbvdd3 supply digital buffer supply h13, k3, l3, m4 dbgnd supply digital buffer ground otp memory d4 progvdd supply high-voltage input for otp programming.
pre-production WM8310 w pp, may 2012, rev 3.1 11 pin name type power domain description dc-dc converters and ldo regulators b1, b2, b3, b13, c3, c4, c7, c8, c9, c10, c11, c12, d3, d6, d12, e3, e4, e12, f4, f5, f6, f10, f11, f12, g4, g6, g7, g8, g9, h7, j10, k9, k10, l8, l9, m1, m6, m7, m8 gnd supply ground a2 pvdd1 supply internal vdd supply; connect to sysvdd n9 pvdd2 supply a10, b10 dc1gnd supply dc-dc1 power ground a13 dc1fb analogue input dc1vdd dc-dc1 feedback pin a11, b11 dc1lx analogue i/o dc-dc1 inductor connection a12, b12 dc1vdd supply dc-dc1 power input (connect to sysvdd supply) a9, b9 dc2gnd supply dc-dc2 power ground c6 dc2fb analogue input dc2vdd dc-dc2 feedback pin a8, b8 dc2lx analogue i/o dc-dc2 inductor connection a7, b7 dc2vdd supply dc-dc2 power input (connect to sysvdd supply) a6, b6, c5 dc3gnd supply dc-dc3 power ground a3 dc3fb analogue input dc3vdd dc-dc3 feedback pin a5, b5 dc3lx analogue i/o dc-dc3 inductor connection a4, b4 dc3vdd supply dc-dc3 power input (connect to sysvdd supply) g13 dc4gnd supply dc-dc4 power ground e11 dc4fb analogue input dc4vdd dc-dc4 feedback connection g12 dc4lx analogue i/o dc-dc4 inductor connection f13 dc4vdd supply dc-dc4 power input (connect to sysvdd supply) l1 ldo1vdd supply ldo1 power input (must be sysvdd supply) l2 ldo1vout analogue output ldo1vdd ldo1 power output k1 ldo2vdd supply ldo2 power input (must be sysvdd supply) k2 ldo2vout analogue output ldo2vdd ldo2 power output j1 ldo3vdd supply ldo3 power input (must be sysvdd supply) j2 ldo3vout analogue output ldo3vdd ldo3 power output e1 ldo4vdd supply ldo4 power input (must be sysvdd supply) e2 ldo4vout analogue output ldo4vdd ldo4 power output d1 ldo5vdd supply ldo5 power input (must be sysvdd supply) d2 ldo5vout analogue output ldo5vdd ldo5 power output c1 ldo6vdd supply ldo6 power input (must be sysvdd supply) c2 ldo6vout analogue output ldo6vdd ldo6 power output h1 ldo7vdd supply ldo7 power input h2 ldo7vout analogue output ldo7vdd ldo7 power output g1 ldo8vdd supply ldo8 power input
WM8310 pre-production w pp, may 2012, rev 3.1 12 pin name type power domain description g3 ldo8vout analogue output ldo8vdd ldo8 power output g2 ldo9vdd supply ldo9 power input f3 ldo9vout analogue output ldo9vdd ldo9 power output f1 ldo10vdd supply ldo10 power input f2 ldo10vout analogue output ldo10vdd ldo10 power output k13 ldo11vout analogue output pvdd ldo11 (alive) power output n10 ldo12vout analogue i/o pvdd ldo12 (internal vpmic) output; backup battery supply input / output e10 ldo13vout analogue i/o pvdd ldo13 (internal intvdd) output; not for general use current sinks m12 isink1 analogue output sysvdd led string current sink 1 l12 isink2 analogue output led string current sink 2 l11, m11 isinkgnd supply led string current sink ground voltage and current references h6 vrefc analogue i/o vpmic voltage reference capacitor connection point j8 irefr analogue i/o current reference resistor connection point l13 refgnd supply reference ground power path management j5, j6 k5, k6, l7, n6 sysvdd supply system vdd supply k7, l5, m5, n8 usbvdd supply usb vdd supply l6, n7 battvdd supply primary battery supply a1 battfetena digital ou tput pvdd external battery fet driver j4 wallvdd supply wall vdd supply/sense k4 wallfetena digital output highest vdd supply external wall fet driver. power domain is the highest out of wallvdd, usbvdd or battvdd. h4 ntcbias analogue output vpmic battery ntc temperature monitor supply h5 ntcmon analogue input battery ntc temperature monitor voltage sense input status led drivers j11 led1 digital output sysvdd status led driver 1. open drain output k11 led2 digital output status led driver 2. open drain output do not connect h3, h9, h10, h11, j13, k12, m2, m3, n1, n2 dnc do not connect
pre-production WM8310 w pp, may 2012, rev 3.1 13 4 thermal characteristics thermal analysis must be performed in the intended application to prevent the WM8310 from exceeding maximum junction temperature. several contributing factors affect thermal performance most notably the physical properties of the mechani cal enclosure, location of the device on the pcb in relation to surrounding components and the number of pcb layers. connecting the gnd balls through thermal vias and into a large ground plane will aid heat extraction. three main heat transfer paths exist to surrounding air: - package top to air (c onvection and radiation). - package bottom to pcb (c onvection and radiation). - package leads to pcb (conduction). (note that radiation is not normally significant at the moderate temperatures experienced in typical applications.) the temperature rise t r is given by t r = p d * ? ja - p d is the power dissipated by the device. - ? ja is the thermal resistance from the juncti on of the die to the ambient temperature and is therefore a measure of heat trans fer from the die to surrounding air. - for WM8310, ? ja = 45 ? c/w - the quoted ? ja is based on testing to the eia/jedec-51-2 test environment (ie. 1ft 3 box, still air, with specific pcb stack-up and tracking rules). note that this is not guaranteed to reflect all typical end applications. the junction temperature t j is given by t j = t a + t r - t a , is the ambient temperature. the worst case conditions are when the WM8310 is operating in a high ambient temperature, and under conditions which caus e high power dissipation, such as t he dc-dc converters operating at low supply voltage, high duty cycle and high output current. under such conditions, it is possible that the heat dissipated could cause the ma ximum junction temperature of the device to be exceeded. care must be taken to avoid this situation. an exampl e calculation of the junc tion temperature is given below. - p d = 500mw (example figure) - ? ja = 45c/w - t r = p d * ? ja = 22.5c - t a = 85c (example figure) - t j = t a +t r = 107.5c the minimum and maximum operating junction temperatures for the WM8310 are quoted in section 5. the maximum junction temperature is 125 c. therefore, the junction temperature in the above example is within the operating limits of the WM8310.
WM8310 pre-production w pp, may 2012, rev 3.1 14 5 absolute maximum ratings absolute maximum ratings are stress ratings only. permanent dam age to the device may be caused by continuously operating at or beyond these limits. device functional operating limits and guarant eed performance specifications are given under electrical characteristics at the te st conditions specified. esd sensitive device. this device is manufactured on a cmos process. it is therefore generically susceptible to damage from excessive static voltages. proper esd pr ecautions must be taken during handling and storage of this device. wolfson tests its package types according to ipc/jedec j-std- 020b for moisture sensitivity to determine acceptable storage conditions prior to surface mount assembly. these levels are: msl1 = unlimited floor life at <30 ? c / 85% relative humidity. not normally stored in moisture barrier bag. msl2 = out of bag storage for 1 year at <30 ? c / 60% relative humidity. supplied in moisture barrier bag. msl3 = out of bag storage for 168 hours at <30 ? c / 60% relative humidity. supplied in moisture barrier bag. the WM8310 has been classified as msl3. condition min max otp programming supply (progvdd) -0.3v 7.0v battvdd, wallvdd and usbvdd supplies -0.3v 7.0v input voltage for ldo regulators -0.3v 7.0v input voltage for dc-dc converters -0.3v 7.0v digital buffer supply (dbvdd1, dbvdd2, dbvdd3) -0.3v 4.5v voltage range for digital inputs -0.3v dbvdd + 0.3v operating temperature range, t a -40 ? c +85 ? c junction temperature, t j -40 ? c +125 ? c thermal impedance junction to ambient, ja 45 ? c/w storage temperature prior to soldering 30 o c max / 60% rh max storage temperature after soldering -65 ? c +150 ? c soldering temperature (10 seconds) +260 ? c note: these ratings assume that all ground pins are at 0v. 6 recommended operating conditions parameter symbol min typ max units wall input power source wallvdd 4.3 5.5 v battery input power source battvdd 2.7 5.5 v usb input power source usbvdd 4.3 5.5 v digital buffer supply dbvdd1, dbvdd2, dbvdd3 1.71 3.6 v otp programming supply (see note) progvdd 6.25 6.5 6.75 v ldo12vout 3.3 v ground gnd, dc1gnd, dc2gnd, dc3gnd, dc4gnd, dbgnd, xoscgnd, refgnd 0 v note: the otp programming supply progvdd should onl y be present when programming the otp. at other times, this pin should be left unconnected. the ldo12vout must be overdriven by an exter nal supply when programming the otp. at other times, the voltage at this pin is driven by t he internal circuits of the WM8310.
pre-production WM8310 w pp, may 2012, rev 3.1 15 7 electrical characteristics 7.1 dc-dc synchronous buck converters dc-dc1 and dc-dc2 unless otherwise noted: v in = 3.8v, v out = 1.2v, mode = fccm (1) , t j = -40c to +125c; typical values are at t j = 25c parameter symbol test conditions min typ max unit input voltage v in v in = sysvdd 2.7 5.5 v programmable output voltage v out f sw = 2mhz 0.6 1.8 v f sw = 4mhz 0.6 1.4 v out step size v out_step 12.5 mv v out accuracy v out_acc v in = 2.7v to 5.5v, i out = 0ma to 1200ma -3 3 % undervoltage margin 0.6v v out < 0.9v 50 mv 0.9v v out < 1.3v 80 1.3v v out 1.8v 100 overvoltage margin 0.6v v out 1.8v 100 mv output current i out fccm (1) and auto (ccm/dcm with ps (2) ) modes 0 1200 ma hysteretic mode 0 150 ldo mode 0 10 p-channel current limit i p_lim f sw = 2mhz 1800 ma f sw = 4mhz 2000 quiescent current i q i out = 0ma, fccm (1) and auto (ccm/dcm with ps (2) ) modes (excluding switching losses) 500 ? a i out = 0ma, hysteretic mode 70 i out = 0ma, ldo mode 25 shutdown current i sd dc m _ena = 0 0.01 ? a p-channel on resistance r dsp v in = v gs = 3.8v, i dcmlx = 100ma 140 m ? n-channel on resistance r dsn v in = v gs = 3.8v, i dcmlx = -100ma 130 m ? switching frequency f sw dc m _freq = 01 2 mhz dc m _freq = 11 4 notes: 1. forced continuous conduction mode 2. continuous / discontinuous c onduction with pulse-skipping mode
WM8310 pre-production w pp, may 2012, rev 3.1 16 dc-dc3 unless otherwise noted: v in = 3.8v, v out = 1.2v, mode = fccm (1) , t j = -40c to +125c; typical values are at t j = 25c parameter symbol test conditions min typ max unit input voltage v in v in = sysvdd 2.7 5.5 v programmable output voltage v out 0.85 (4) 3.4 v v out step size v out_step 25 mv v out accuracy v out_acc v in = 2.7v to 5.5v, i out = 0ma to 1000ma -4 4 % undervoltage margin 0.85v v out 3.4v 50 mv output current i out fccm (1) and auto (ccm/dcm with ps (2) ) modes 0 1000 ma hysteretic mode, dc3_stnby_lim=01 0 200 (3) ldo mode 0 10 p-channel current limit i p_lim 1600 ma quiescent current i q i out = 0ma, fccm (1) and auto (ccm/dcm with ps (2) ) modes (excluding switching losses) 330 ? a i out = 0ma, hysteretic mode 110 i out = 0ma, ldo mode 30 shutdown current i sd dc3_ena = 0 0.01 ? a p-channel on resistance r dsp v in = v gs = 3.8v, i dc3lx = 100ma 165 m ? n-channel on resistance r dsn v in = v gs = 3.8v, i dc3lx = -100ma 155 m ? switching frequency f sw 2 mhz notes: 1. forced continuous conduction mode 2. continuous / discontinuous c onduction with pulse-skipping mode 3. the maximum output current in hyst eretic mode can be adjusted using the dc m _stnby_lim registers 4. in fccm mode, the minimum v out is 1.2v
pre-production WM8310 w pp, may 2012, rev 3.1 17 7.2 dc-dc step up converter dc-dc4 unless otherwise noted: v in = 3.8v, t j = -40c to +125c; typical values are at t j = 25c parameter symbol test conditions min typ max unit input voltage v in v in = sysvdd 2.7 5.5 v output voltage v out 6.5 30 v load current i load v out 8v 0 90 ma v out = 6.5v to 20v 0 40 v out = 20v to 30v 0 25 quiescent current i q dc4_ena=1 330 ? a shutdown current i sd dc4_ena=0 0.1 1 ? a n-channel on resistance r dsn 150 m ? regulated feedback voltage v isinkn 500 mv out of regulation level v isinkn 440 mv overvoltage detection v dc4fb 500 mv switching frequency f sw 1 mhz n-channel current limit i n_lim 800 ma 7.3 current sinks unless otherwise noted: t j = -40c to +125c; typical values are at t j = +25oc parameter symbol test conditions min typ max unit sink current i isinkn 0.3 <= v isinkn <= sysvdd 2 28000 ? a current accuracy i isinkn i isinkn =12ma, v isinkn = 0.5v tbd v current matching i isinkn i isinkn =12ma, v isinkn = 0.5v tbd
WM8310 pre-production w pp, may 2012, rev 3.1 18 7.4 ldo regulators ldo1 unless otherwise noted: v in = 3.8v, v out = 1.8v, t j = -40c to +125c; typical values are at t j = +25oc parameter symbol test conditions min typ max unit input voltage v in v in sysvdd 1.5 5.5 v programmable output voltage v out 0.9 3.3 v v out step size v out_step v out = 0.9v to 1.6v 50 mv v out = 1.7v to 3.3v 100 output current i out normal mode 0 300 ma low power mode, ldo n _lp_mode=0 0 50 low power mode, ldo n _lp_mode=1 0 20 v out accuracy v out_acc i load = 1ma -3 +3 % line regulation v out line v in = (v out + 0.5) to 5.5v, i load = 150ma note that v in must be >= 1.5v 0.1 %/v load regulation v out load i load =1ma to 300ma 0.015 %/ma dropout voltage v in - v out i load =150ma, v out > 2.7v 250 mv i load =150ma, v out 1.8v to 2.7v 300 i load =150ma, v out < 1.8v 500 undervoltage level v out v out falling 88 % quiescent current i q normal mode, no load 30 ? a low power mode, ldo n _lp_mode=0, no load 10 low power mode, ldo n _lp_mode=1, no load 5 i load = 1ma to 300ma i q (no load) + 1% of load power supply rejection ratio psrr i load = 150ma, <= 1khz 53 db i load = 150ma, 10khz 53 i load = 150ma, 100khz 32 on resistance (switch mode) r dson v in = 1.5v, i load = 100ma 1.5 ? v in = 1.8v, i load = 100ma 1.2 v in = 2.5v, i load = 100ma 0.85 v in = 3.3v, i load = 100ma 0.7 current limit (switch mode) i cl v out = 0v 600 ma start-up time t start_up no load, output cap 2.2 f, 90% of v out 10 ? s shutdown time t shut_down no load, output cap 2.2 f, 10% of v out 10 ms ldo2, ldo3 unless otherwise noted: v in = 3.8v, v out = 1.8v, t j = -40c to +125c; typical values are at t j = +25oc parameter symbol test conditions min typ max unit input voltage v in v in sysvdd 1.5 5.5 v programmable output voltage v out 0.9 3.3 v v out step size v out_step v out = 0.9v to 1.6v 50 mv v out = 1.7v to 3.3v 100 output current i out normal mode 0 200 ma low power mode, ldo n _lp_mode=0 0 50 low power mode, ldo n _lp_mode=1 0 20 v out accuracy v out_acc i load = 1ma -3 +3 % line regulation v out line v in = (v out + 0.5) to 5.5v, i load = 100ma note that v in must be >= 1.5v 0.1 %/v load regulation v out load i load =1ma to 200ma 0.015 %/ma
pre-production WM8310 w pp, may 2012, rev 3.1 19 parameter symbol test conditions min typ max unit dropout voltage v in - v out i load =100ma, v out > 2.7v 200 mv i load =100ma, v out 1.8v to 2.7v 250 i load =100ma, v out < 1.8v 400 undervoltage level v out v out falling 88 % quiescent current i q normal mode, no load 30 ? a low power mode, ldo n _lp_mode=0, no load 10 low power mode, ldo n _lp_mode=1, no load 5 i load = 1ma to 200ma i q (no load) + 1% of load power supply rejection ratio psrr i load = 100ma, <= 1khz 55 db i load = 100ma, 10khz 55 i load = 100ma, 100khz 32 on resistance (switch mode) r dson v in = 1.5v, i load = 100ma 1.5 ? v in = 1.8v, i load = 100ma 1.2 v in = 2.5v, i load = 100ma 0.85 v in = 3.3v, i load = 100ma 0.7 current limit (switch mode) i cl v out = 0v 400 ma start-up time t start_up no load, output cap 2.2 f, 90% of v out 10 ? s shutdown time t shut_down no load, output cap 2.2 f, 10% of v out 10 ms ldo4, ldo5, ldo6 unless otherwise noted: v in = 3.8v, v out = 1.8v, t j = -40c to +125c; typical values are at t j = +25oc parameter symbol test conditions min typ max unit input voltage v in v in sysvdd 1.5 5.5 v programmable output voltage v out 0.9 3.3 v v out step size v out_step v out = 0.9v to 1.6v 50 mv v out = 1.7v to 3.3v 100 output current i out normal mode 0 100 ma low power mode, ldo n _lp_mode=0 0 50 low power mode, ldo n _lp_mode=1 0 20 v out accuracy v out_acc i load = 1ma -3 +3 % line regulation v out line v in = (v out + 0.5) to 5.5v, i load = 50ma note that v in must be >= 1.5v 0.1 %/v load regulation v out load i load =1ma to 100ma 0.025 %/ma dropout voltage v in - v out i load =100ma, v out > 2.7v 200 mv i load =100ma, v out 1.8v to 2.7v 250 i load =100ma, v out < 1.8v 400 undervoltage level v out v out falling 88 % quiescent current i q normal mode, no load 30 ? a low power mode, ldo n _lp_mode=0, no load 10 low power mode, ldo n _lp_mode=1, no load 5 i load = 1ma to 100ma i q (no load) + 1% of load power supply rejection ratio psrr i load = 50ma, <= 1khz 55 db i load = 50ma, 10khz 55 i load = 50ma, 100khz 32 on resistance (switch mode) r dson v in = 1.5v, i load = 100ma 3.2 ? v in = 1.8v, i load = 100ma 2.1 v in = 2.5v, i load = 100ma 1.35 v in = 3.3v, i load = 100ma 1.1
WM8310 pre-production w pp, may 2012, rev 3.1 20 parameter symbol test conditions min typ max unit current limit (switch mode) i cl v out = 0v 230 ma start-up time t start_up no load, output cap 2.2 f, 90% of v out 10 ? s shutdown time t shut_down no load, output cap 2.2 f, 10% of v out 10 ms ldo7, ldo8 unless otherwise noted: v in = 3.8v, v out = 1.8v, t j = -40c to +125c; typical values are at t j = +25oc parameter symbol test conditions min typ max unit input voltage v in 1.71 5.5 v programmable output voltage v out 1.0 3.5 v v out step size v out_step v out = 1.0v to 1.6v 50 mv v out = 1.7v to 3.5v 100 output current i out normal mode 0 200 ma low power mode 0 50 v out accuracy v out_acc i load = 1ma -2.5 +2.5 % line regulation v out line v in = (v out + 0.5) to 5.5v, i load = 100ma note that v in must be >= 1.71v 0.025 %/v load regulation v out load i load =1ma to 200ma 0.003 %/ma dropout voltage v in - v out i load =100ma, v out =1.8v 95 mv i load =100ma, v out =2.5v 65 i load =100ma, v out =3.3v 60 undervoltage level v out v out falling 93 % quiescent current i q normal mode, no load 110 ? a low power mode, no load 70 i load = 1ma to 200ma i q (no load) + 0.1% of load power supply rejection ratio psrr i load = 100ma, <= 1khz 70 db i load = 100ma, 10khz 67 i load = 100ma, 100khz 48 output noise voltage v out f=10hz to 100khz; v out =2.8v, i load = 1ma 30 ? v rms f=10hz to 100khz; v out =2.8v, i load = 10ma 32 f=10hz to 100khz; v out =2.8v, i load = 100ma 32 on resistance (switch mode) r dson v in = 1.71v, i load = 100ma 550 m ? v in = 1.8v, i load = 100ma 500 v in = 2.5v, i load = 100ma 330 v in = 3.5v, i load = 100ma 250 current limit (switch mode) i cl v out = 0v 320 ma start-up time t start_up no load, output cap 4.7 f, 90% of v out 50 ? s shutdown time t shut_down no load, output cap 4.7 f, 10% of v out 10 ms ldo9, ldo10 unless otherwise noted: v in = 3.8v, v out = 1.8v, t j = -40c to +125c; typical values are at t j = +25oc parameter symbol test conditions min typ max unit input voltage v in 1.71 5.5 v programmable output voltage v out 1.0 3.5 v v out step size v out_step v out = 1.0v to 1.6v 50 mv v out = 1.7v to 3.5v 100 output current i out normal mode 0 150 ma low power mode 0 50
pre-production WM8310 w pp, may 2012, rev 3.1 21 parameter symbol test conditions min typ max unit v out accuracy v out_acc i load = 1ma -2.5 +2.5 % line regulation v out line v in = (v out + 0.5) to 5.5v, i load = 75ma note that v in must be >= 1.71v 0.025 %/v load regulation v out load i load =1ma to 150ma 0.004 %/ma dropout voltage v in - v out i load =100ma, v out =1.8v 135 mv i load =100ma, v out =2.5v 100 i load =100ma, v out =3.3v 90 undervoltage level v out v out falling 93 % quiescent current i q normal mode, no load 110 ? a low power mode, no load 70 i load = 1ma to 150ma i q (no load) + 0.1% of load power supply rejection ratio psrr i load = 75ma, <= 1khz 73 db i load = 75ma, 10khz 69 i load = 75ma, 100khz 49 output noise voltage v out f=10hz to 100khz; v out =2.8v, i load = 1ma 30 ? v rms f=10hz to 100khz; v out =2.8v, i load = 10ma 32 f=10hz to 100khz; v out =2.8v, i load = 100ma 32 on resistance (switch mode) r dson v in = 1.71v, i load = 100ma 1000 m ? v in = 1.8v, i load = 100ma 930 v in = 2.5v, i load = 100ma 610 v in = 3.5v, i load = 100ma 430 current limit (switch mode) i cl v out = 0v 250 ma start-up time t start_up no load, output cap 4.7 f, 90% of v out 70 ? s shutdown time t shut_down no load, output cap 4.7 f, 10% of v out 10 ms ldo11 unless otherwise noted: v in = 3.8v, v out = 1.2v, t j = -40c to +125c; typical values are at t j = +25oc parameter symbol test conditions min typ max unit programmable output voltage v out 0.8 1.55 v v out step size v out_step 50 mv output current i out sysvdd < 3.1v 0 10 ma sysvdd 3.1v 0 25 v out accuracy v out v in = 2.7 to 5.5v ; i load = 100a -4 +4 % line regulation v out line v in = 2.7 to 5.5v; i load = 1ma 0.4 %/v load regulation v out load i load = 100a to 10ma 0.2 %/ma quiescent current i q no load 2.5 ? a start-up time t start_up no load, output cap 0.1 f, 90% of v out 0.3 1 ms shutdown time t shut_down no load, output cap 0.1 f, 10% of v out 0.3 1 ms
WM8310 pre-production w pp, may 2012, rev 3.1 22 7.5 reset thresholds unless otherwise noted: t j = -40c to +125c; typical values are at t j = +25oc parameter symbol test conditions min typ max unit power on reset power on reset threshold vpmic (ldo12vout) voltage at which device transitions between no power and backup states v por, de- assert vpmic rising 1.18 v v por, assert vpmic falling 1.08 v power on reset hysteresis v por, hyst 100 mv device reset control device reset threshold vpmic (ldo12vout) voltage at which device transitions between backup and off states v res, de- assert vpmic rising 1.94 v v res, assert vpmic falling 1.85 v device reset hysteresis v res, hyst 92 mv device shutdown shutdown threshold sysvdd voltage at which the device forces an off transition v shutdown sysvdd falling 2.7 v syslo threshold accuracy sysvdd voltage at which syslo is asserted v syslo sysvdd falling, v syslo set by syslo_thr (2.8v to 3.5v) -3.5 +3.5 % sysok threshold accuracy sysvdd voltage at which sysok is asserted. v sysok sysvdd rising, v sysok set by sysok_thr (2.8v to 3.5v) note the sysok hysteresis margin (v sysok, hyst ) is added to sysok_thr. -3.5 +3.5 % sysok hysteresis v sysok, hyst 40 mv 7.6 references unless otherwise noted: t j = +25oc parameter symbol test conditions min typ max unit voltage reference v vrefc 0.8 v current reference v irefr 100k ? to refgnd 0.5 v
pre-production WM8310 w pp, may 2012, rev 3.1 23 7.7 battery charger unless otherwise noted: t j = -40c to +125c; typical values are at t j = +25oc parameter symbol test conditions min typ max unit general supply voltage (voltage required to commence charging; note that charging can continue at lower supply voltages, eg. under current throttling conditions) v sysvdd 4.3 5.5 v target voltage v batt_tgt chg_vsel = 00 4.0 4.05 4.1 v chg_vsel = 01 4.05 4.10 4.15 chg_vsel = 10 4.1 4.15 4.2 chg_vsel = 11 4.15 4.20 4.25 charger re-start threshold (trickle charging starts when battery voltage is below this threshold) v batt_rstrt v batt_tgt - 100mv v defective battery threshold v batt_def 2.85 v defective battery timeout t batt_def 30 mins overvoltage threshold v batt_ov 4.5 v end of charge current i eoc set by chg_iterm 20 to 90 ma maximum trickle charge current i trkl_lim set by chg_trkl_ilim 50 to 200 ma fast charge threshold (fast charging fast-charge is only possible when battery voltage is above this threshold) v fast_chg 2.85 v maximum fast charge current i fast_lim set by chg_fast_ilim 50 to 1000 ma supply voltage regulation level (current throttling is applied if supply drops to this level) v sys_reg internal battery fet ?on? resistance r chg_sw v battvdd = 3.8v 90 m ? v battvdd = 3.3v 100 battery temperature monitoring battery temperature monitor source (ntcbias) v ntcbias 2.1 v ntcmon voltage for high battery temperature detection v btemp_h v ntcmon falling 0.344 ? v ntcbias v v ntcmon rising 0.365 ? v ntcbias ntcmon voltage for low battery temperature detection v btemp_l v ntcmon rising 0.767 ? v ntcbias v v ntcmon falling 0.743 ? v ntcbias ntcmon voltage for ?no ntc? detection v no_ntc v ntcmon rising 0.961 ? v ntcbias v v ntcmon falling 0.931 ? v ntcbias
WM8310 pre-production w pp, may 2012, rev 3.1 24 7.8 usb power control unless otherwise noted: t j = -40c to +125c; typical values are at t j = +25oc parameter symbol test conditions min typ max unit supply voltage v usbvdd 4.3 5.5 v usb fet ?on? resistance r usb_sw usb_ilim = 010 230 m ? usb_ilim = 011 or greater 96 current limit i usbvdd usb_ilim = 010 91 100 ma usb_ilim = 011 454 500 usb_ilim = 100 805 900 usb_ilim = 101 1343 1500 usb_ilim = 110 1609 1800 usb_ilim = 111 496 550 current limit response time 10 ? s 7.9 general purpose inputs / outputs (gpio) unless otherwise noted: t j = -40c to +125c; typical values are at t j = +25oc parameter symbol test conditions min typ max unit gpio1, gpio2, gpio3, gpio7, gpio8, gpio9 input high level v ih 0.75 x vdd v input low level v il 0.25 x vdd v output high level v oh i oh = 1ma 0.8 x vdd v output low level v ol i ol = -1ma 0.2 x vdd v pull-up resistance to vdd r pu gpn_pwr_dom=0 and dbvdd=1.8v or gpn_pwr_dom=1 180 k ? pull-down resistance r pd 180 k ? gpio4, gpio5, gpio6, gpio10, gpio11, gpio12 input high level v ih 0.85 x vdd v input low level v il 0.2 x vdd v output high level v oh i oh = 1ma 0.8 x vdd v output low level v ol i ol = -1ma 0.2 x vdd v pull-up resistance to vdd r pu gpn_pwr_dom=0 and dbvdd=1.8v or gpn_pwr_dom=1 and sysvdd=3.8v 180 k ? pull-down resistance r pd 180 k ? notes: 1. ?vdd? is the voltage of the applicable power domain for eac h pin (selected by the corres ponding gpn_pwr_dom register). 2. pull-up / pull-down resistance only applies when enabled using the gpn_pull registers. 3. pull-up / pull-down resistors are dis abled when the gpio pin is tri-stated. 4. pull-up / pull-down resistance may change with the app licable power domain (as selected by gpn_pwr_dom).
pre-production WM8310 w pp, may 2012, rev 3.1 25 7.10 digital interfaces unless otherwise noted: t j = -40c to +125c; typical values are at t j = +25oc parameter symbol test conditions min typ max unit on , reset , irq , cifmode, sdout1, sclk1, sda1, cs , sclk2, sda2 input high level v ih 0.75 x vdd v input low level v il 0.2 x vdd v output high level v oh i oh = 1ma 0.8 x vdd v output low level v ol i ol = -1ma 0.2 x vdd v ?vdd? is the voltage of the applicable power dom ain for each pin, as defined in section 3. on pin pull-up resistance r pu 140 k ? reset pin pull-up resistance r pu dbvdd=1.8v 180 k ? dbvdd=3.6v 85 irq pin pull-up resistance r pu dbvdd=1.8v 180 k ? dbvdd=3.6v 85 sclk2 pin pull-down resistance r pd 100 k ? sda2 pin pull-down resistance r pd 100 k ? 7.11 auxiliary adc unless otherwise noted: t j = +25oc parameter symbol test conditions min typ max unit input resistance r auxadcinn during measurement 400 k ? input voltage range v auxadcin1, 2, 3 0 v sysvdd v v auxadcin4 0 v dbvdd input capacitance c auxadcinn 2 pf auxadc resolution 12 bits auxadc conversion time 39 ? s auxadc accuracy input voltage = 3v -2.5 +2.5 % 7.12 system status led drivers unless otherwise noted: t j = +25oc parameter symbol test conditions min typ max unit led1 and led2 sink current 10 ma 7.13 clocking unless otherwise noted: t j = +25oc parameter symbol test conditions min typ max unit fll input reference 32.768khz fll_clk_src=00 32.768 khz clkin fll_clk_src=01 32 25000 khz fll output frequency clkout clkout_src=0 32 25000 khz
WM8310 pre-production w pp, may 2012, rev 3.1 26 8 typical power consumption data to follow
pre-production WM8310 w pp, may 2012, rev 3.1 27 9 typical performance data 9.1 dc-dc converters data to follow 9.2 ldo regulators data to follow
WM8310 pre-production w pp, may 2012, rev 3.1 28 10 signal timing requirements 10.1 control interface figure 1 control interface timing - 2-wire (i2c) control mode test conditions t j = -40oc to +125 oc unless otherwise stated. parameter symbol min typ max unit sclk1 frequency 0 400 khz sclk1 low pulse-width t 1 1300 ns sclk1 high pulse-width t 2 600 ns hold time (start condition) t 3 600 ns setup time (start condition) t 4 600 ns data setup time t 5 100 ns sda1, sclk1 rise time t 6 300 ns sda1, sclk1 fall time t 7 300 ns setup time (stop condition) t 8 600 ns data hold time t 9 900 ns pulse width of spikes that will be suppressed t ps 0 5 ns
pre-production WM8310 w pp, may 2012, rev 3.1 29 figure 2 control interface timing - 4-wire (spi) control mode (write cycle) sclk1 (input) sdout1 (output) t dl cs (input) figure 3 control interface timing - 4-wire (spi) control mode (read cycle) test conditions t j = -40oc to +125 oc unless otherwise stated. parameter symbol min typ max unit cs falling edge to sclk1 rising edge t csu 40 ns sclk1 falling edge to cs rising edge t cho 10 ns sclk1 pulse cycle time t scy 200 ns sclk1 pulse width low t scl 80 ns sclk1 pulse width high t sch 80 ns sda1 to sclk1 set-up time t dsu 40 ns sda1 to sclk1 hold time t dho 10 ns pulse width of spikes that will be suppressed t ps 0 5 ns sclk1 falling edge to sdout1 transition t dl 40 ns the cs pin must be held high for at least 1 ? s after every register write operation in spi mode.
WM8310 pre-production w pp, may 2012, rev 3.1 30 11 device description 11.1 general description the WM8310 is a multi-purpose power management dev ice with a comprehensive range of features. the WM8310 provides 4 dc-dc conv erters and 11 ldo regulators which are all programmable to application-specific requirements. the on-boar d oscillator and two additional ldos support the clocking and control functions fo r the dc-dc converters and other core functions. the device has flexible power supply options, wh ich enable hot-switching between exte rnal supplies (wall adaptor or usb), or a battery. the WM8310 provides a configur able charger for the main battery and maintains the backup power source using a constant-voltage output. other f eatures include 2 current sinks (led drivers), flexible gpio capability, and led outputs for system status indications. the WM8310 also provides a 32.768khz crystal osc illator and secure real time clock (srtc). the frequency locked loop (fll) enables different clo ck frequencies to be generated from the 32khz reference to provide clocking for external circuits. an auxiliary a dc is included, for measurement of internal and external voltages. under typical operating conditions , the device is powered up and shut down under the control of the on pin. the device executes a programmabl e sequence of enabling or disabling the dc-dc converters, ldos and other func tions when commanded to power up or shut down respectively. an alternate device state (sleep power state) is provided, in which selected functions may be separately configured for a low-power or other oper ating condition. the configuration of the normal operating state may be programmed into an integrat ed otp non-volatile memory. if desired, the otp memory can be programmed during device manufacture in accordance with the user?s specification. see section 14 for details of the otp and a ssociated bootstrap configuration functions. in the absence of suitable power supplies, the WM8310 automatically reverts to a backup state, under which a minimal functionality is maintained to enable a smooth return to normal operation when the supplies are restored. with a backup supply presen t, the rtc is updated in the backup state, allowing the main battery to be depleted or changed without loss of rtc function. without a backup battery, a small capacitor is sufficient to maintain the rtc (unclocked) for up to 5 minutes. 11.2 power states the WM8310 has 6 main power states, which are descr ibed below. different levels of functionality are associated with each of the power states. some of the state transitions are made autonomously by the WM8310 (eg. transitions to/from backup are sc heduled according to the available power supply conditions). other transitions are init iated as a result of instructions issued over the control interface or as a result of software functions (eg. wa tchdog timer) or hardware f unctions such as the on pin. the valid transitions and the associ ated conditions are detailed below. no power - this is the device state when no power is available. all functi ons are disabled and all register data is lost. off - this is the device state when power is ava ilable but the device is switched off. the rtc is enabled and the register map contents are maintained. the reset pin is pulled low in this state. ldo11 may optionally be enabled in this state; all other dc-dcs and ldos are disabled (except ldo12, which supports internal functions). on - this is the normal operating state when the device is switched on. all device functions are available in this state. sleep - this is a user-configurabl e operating state which is intended for a low-power operating condition. selected functions ma y be enabled, disabled or re-confi gured according to the user?s requirements. a programmable configuration sequence for the dc-dcs and ldos is executed on transition to/from sleep mode. backup - this is the operating state when the av ailable power supplies are below the reset threshold of the device. typically, this means that usb or wall supplies are not present and that the main battery is either discharged or removed. all dc-dc converters and ld o regulators are disabled in this state. the rtc and oscillator and a ?softw are scratch? memory area can be maintained from the backup supply (if available) in this state. a ll other functions and registers are reset in backup. (note that, for power saving, an ?unclocked? m ode, in which the rtc is held constant, may be selected if required.)
pre-production WM8310 w pp, may 2012, rev 3.1 31 program - this is a special operating state whic h is used for programming the integrated otp memory with the device configuration data. t he settings stored in the otp define the device configuration in the on state, and also the time/sequencing data associated with on/off power state transitions. see section 14 for details of the otp features. the valid power state transitions are illustrated in figure 4. figure 4 power states and transitions state transitions to/from the no power state are controlled automatically by the internal supply (vpmic) voltage generated by ldo12. the device is in the no power state when this voltage is below the power-on reset (por) threshold. see section 24 for more details on power-on reset. state transitions to/from the backup state are c ontrolled automatically by the internal supply (vpmic) voltage generated by ldo12. the device is in the backup state when this voltage is below the device reset threshold. see section 24 for more details on resets. state transitions to/from the program state are required to follow specif ic control sequences. see section 14 for details of the program functions.
WM8310 pre-production w pp, may 2012, rev 3.1 32 the remaining transitions between the off, on and sleep states may be initiated by a number of different mechanisms - some of them automatic, so me of them user-controlled. transitions between these states are time-controll ed sequences of events. these are the off, on, sleep and wake sequences shown in figure 4. t hese transitions are programmabl e, using data stored in the integrated otp memory or else data loaded from an external instantconfig? eeprom (ice) memory. see section 14 for details. note that a transition from the sleep state to the off state is not a controlled transition. if an ?off? event occurs whilst in the sleep state, then the WM8310 will select the off state, but all the enabled converters and regulators w ill be disabled immediately; the time-controlled sequence is not implemented in this case. see section 11.3 for details of the WM8310 ?off? events. the current power state of the WM8310 can be read from the main_state register field. a restricted definition of this field is shown in table 1. note that other values of main_state are defined for transition states, but it is recommended that only the values quoted below should be used to confirm power state transitions. a power state transition to the backup, sleep, on or off state is indicated by the interrupt bits described in section 11.4. address bit label default description r16397 (400dh) system status 4:0 main_state [4:0] 0_0000 main state machine condition 0_0000 = off 0_1011 = program 1_1100 = sleep 1_1111 = active (on) table 1 power state readback 11.3 power state control the off, on, sleep and wake sequences are initiat ed by many different conditions. when such a condition occurs, the WM8310 sc hedules a series of 5 timeslots, enabling a sequence of enable/disable events to be controlled. the nominal duration of the timeslots is fixed at 2ms, though this may be extended if any selected circuit has not st arted up within this time, as described later in this section. the off, sleep and wake sequences commence after a programmable delay set by pwrstate_dly. this allows a host processo r to request a WM8310 state transition and then complete other tasks before the transition actually occurs. the on sequence is the transition from off to on power states. each ldo and each dc-dc converter (except dc-dc4) may be associated with any one of the available timeslots in the on sequence. this determines the time, within the s equence, at which that dc-dc converter or ldo will be enabled following an ?on? event. the clock output (clkout) and gpio pins confi gured as external power enable (epe) outputs can also be associated with any one of the available ti meslots in the on sequence. the epe function is a logic output that may be used to control external circuits, including exte rnal dc-dc converters. an example ?on? state transition sequence is illu strated in figure 5. each of the dc-dc buck converters and ldo regulators can be individually assigned to one of the five timeslots (shown as t1, t2, t3, t4, t5), providing total flexibility in the power sequence.
pre-production WM8310 w pp, may 2012, rev 3.1 33 figure 5 example control sequence for ?on? state transition the possible ?on? events that may trigger the on sequence are listed in table 3. the on sequence is only permitted when the supply voltage sysvdd ex ceeds a programmable threshold sysok. see section 24 for details of sysvdd voltage monitoring. the off sequence is the reverse of the on sequenc e. each dc-dc converter, ldo regulator or gpio output that is associated with a timeslot in the on sequence is switched off in the reverse sequence following an ?off? event. if clkout is a ssigned to a timeslot in the on sequence, then this is disabled in the reverse (off) sequence also. the possible ?off? events are listed in table 3. note that it is possible to modify the off sequence by writing to the associated registers in the on pow er state if required; this allows the off sequence to be independent of the on sequence. the sleep sequence is the transition from on to sleep power states. each ldo and each dc-dc converter (except dc-dc4) may be associated with any one of the available timeslots in the sleep sequence. this determines the time, within the s equence, at which that dc converter or ldo will be disabled following a ?sleep? event. the clock output (clkout) and gpio pins confi gured as external power enable (epe) outputs can also be associated with any one of the availabl e timeslots in the sleep sequence. the possible ?sleep? events are listed in table 3. the wake sequence is the reverse of the sleep s equence. each dc-dc converter, ldo regulator or gpio output that is associated with a time slot in the sleep sequence is switched on in the reverse sequence following a ?wake? event. if clko ut is assigned to a timeslot in the sleep sequence, then this is disabled in the reverse (wake) sequence also. the possible ?wake? events are listed in table 3. note that it is possible to modify the wake sequence by writing to the associated registers in t he sleep power state if required; this allows the wake sequence to be independent of the sleep sequence. any dc-dc converter or ldo that is not associat ed with one of the 5 timeslots in the on sequence may, instead, be configured to be hardware contro lled via a gpio pin configured as one of the hardware enable inputs. see section 21 for details of the gpio functions. any dc-dc converter or ldo that is not under hardware control may be enabl ed or disabled under software control in the on state, regardless of whether it is associated with any timeslot in the on sequence. when a valid off event occurs, any dc-dc converter or ldo which is not allocated a timeslot in the on sequence is disabled immediat ely. this includes any dc-dc c onverter or ldo which is under gpio (hardware enable) control. the only except ion is ldo11 which may, optionally, be configured to be enabled in the off state.
WM8310 pre-production w pp, may 2012, rev 3.1 34 the WM8310 monitors the dc-dc converters and ldos during the on sequence to ensure that the required circuits have powered up successfully befor e proceeding to the next timeslot. the nominal timeslot durations are extended if necessary in or der to wait for the selected dc-dc converters or ldos to power up. if the on sequence has not comple ted within 2 seconds of starting the transition, then a power sequence failure has occurred, resulting in the off state being forced. note that, when the off state is forced as a resu lt of a power sequence failure, all converters and regulators will be shut down. the shutdown sequenc e is not controlled in this case; all enabled converters and regulators will be disabled immediately on detecti on of a power sequence failure. the most recent on or wake event can be deter mined by reading the bits in the ?on source? register, r400eh. the most recent off event can be determined by reading the bits in the ?off source? register, r400fh. the ?on source? register is updated when a new on event occurs. the ?off source? register is updated when a new off event occurs. note that some reset conditions (see section 24) result in an off transition followed by an on transition; thes e events are recorded as reset events in the ?on source? register. the on source and off source regist er fields are defined in table 2. address bit label default description r16387 (4003h) power state 15 chip_on 0 indicates whether the system is on or off. 0 = off 1 = on (or sleep) off can be commanded by writing chip_on = 0. note that writing chip_on = 1 is not a valid ?on? event, and will not trigger an on transition. 14 chip_slp 0 indicates whether the system is in the sleep state. 0 = not in sleep 1 = sleep wake can be commanded by writing chip_slp = 0. sleep can be commanded by writing chip_slp = 1. 11:10 pwrstate_dly 10 power state transition delay 00 = no delay 01 = no delay 10 = 1ms 11 = 10ms r16398 (400eh) on source 15 on_trans 0 most recent on/wake event type 0 = wake transition 1 = on transition 11 on_gpio 0 most recent on/wake event type 0 = not caused by gpio input 1 = caused by gpio input 10 on_syslo 0 most recent wake event type 0 = not caused by sysvdd 1 = caused by syslo threshold. note that the syslo threshold cannot trigger an on event. 8 on_chg 0 most recent wake event type 0 = not caused by battery charger 1 = caused by battery charger 7 on_wdog_to 0 most recent wake event type 0 = not caused by watchdog timer 1 = caused by watchdog timer
pre-production WM8310 w pp, may 2012, rev 3.1 35 address bit label default description 6 on_sw_req 0 most recent wake event type 0 = not caused by software wake 1 = caused by software wake command (chip_slp = 0) 5 on_rtc_alm 0 most recent on/wake event type 0 = not caused by rtc alarm 1 = caused by rtc alarm 4 on_on_pin 0 most recent on/wake event type 0 = not caused by the on pin 1 = caused by the on pin 3 reset_cnv_uv 0 most recent on event type 0 = not caused by undervoltage 1 = caused by a device reset due to a converter (ldo or dc-dc) undervoltage condition 2 reset_sw 0 most recent on event type 0 = not caused by software reset 1 = caused by software reset 1 reset_hw 0 most recent on event type 0 = not caused by hardware reset 1 = caused by hardware reset 0 reset_wdog 0 most recent on event type 0 = not caused by the watchdog 1 = caused by a device reset triggered by the watchdog timer r16399 (400fh) off source 13 off_intldo_err 0 most recent off event type 0 = not caused by ldo13 error condition 1 = caused by ldo13 error condition 12 off_pwr_seq 0 most recent off event type 0 = not caused by power sequence failure 1 = caused by a power sequence failure 11 off_gpio 0 most recent off event type 0 = not caused by gpio input 1 = caused by gpio input 10 off_sysvdd 0 most recent off event type 0 = not caused by sysvdd 1 = caused by the syslo or shutdown threshold 9 off_therr 0 most recent off event type 0 = not caused by temperature 1 = caused by over-temperature 6 off_sw_req 0 most recent off event type 0 = not caused by software off 1 = caused by software off command (chip_on = 0) 4 off_on_pin 0 most recent off event type 0 = not caused by the on pin 1 = caused by the on pin table 2 power state control registers
WM8310 pre-production w pp, may 2012, rev 3.1 36 table 3 lists all of the events which can trigger an on, wake, off or sleep transition sequence. it also lists the associated status bits of the ?o n source? and ?off source? register bits which are asserted under each condition. transition sequence event notes on source / off source on (see note 1) rtc alarm an on request occurs if the rtc alarm occurs in the off power state. see section 20. on_trans, on_rtc_alm gpio on request requires a gpio to be configured as ?power on request? or ?power on/off request?. see section 21. on_trans, on_gpio on pin request requires the on pin to be configured to generate on request. see section 11.6. on_trans, on_on_pin wake software wake writing chip_slp = 0. see table 2. on_sw_req battery charger event occurs when a charger interrupt event is triggered. see section 17.7.8. on_chg watchdog timeout requires the watchdog to be configured to generate wake request. see section 25. on_wdog_to rtc alarm a wake request occurs if the rtc alarm occurs in the sleep power state. see section 20. on_rtc_alm gpio wake request requires a gpio to be configured as ?sleep/wake request?. see section 21. on_gpio sysvdd undervoltage requires the sysvdd monitor circuit to be configured to generate wake request. see section 24.4. on_syslo on pin request requires the on pin to be configured to generate wake request. see section 11.6. on_on_pin off (see note 2) watchdog timeout requi res the watchdog to be configured to generate device reset. see section 25. reset_wdog (see note 3) hardware reset see section 24. reset_hw (see note 3) software reset see section 24. reset_sw (see note 3) power management undervoltage reset configurable option for each ldo/dc-dc converter. see section 15. reset_cnv_uv (see note 3) software off request writing chip_on = 0. see table 2. off_sw_req on pin request requires the on pin to be configured to generate off request. see section 11.6. off_on_pin thermal shutdown see section 26. off_therr sysvdd undervoltage requires the sysvdd monitor circuit to be configured to generate off request. see section 24.4. off_sysvdd sysvdd shutdown sysvdd has fallen below the shutdown threshold. see section 24.4. off_sysvdd gpio off request requires a gpio to be configured as ?power on/off request?. see section 21. off_gpio power sequence failure dc-dc converte rs, ldos or clkout circuits (including fll) have failed to start up within the permitted time. off_pwr_seq internal ldo error error condition detected in ldo13 off_intldo_err sleep software sleep request writing chip_slp = 1. see table 2. see note 4 and note 5 gpio sleep request requires a gpio to be configured as ?sleep request? or ?sleep/wake request?. see section 21. see note 4 and note 5 table 3 power state transition events
pre-production WM8310 w pp, may 2012, rev 3.1 37 notes: 1. an on sequence is only permitted when the supply voltage sysvdd exceeds a programmable threshold v sysok . see section 24.4 for details of sysvdd voltage monitoring. 2. selected off events may be masked during battery charging using the chg_off_mask bit. this allows user-initiated off events (software off, on pin request, gpio off request) to be inhibited. see section 17.7.2. 3. these reset conditions result in an o ff transition followed by an on transition. these events are recorded as reset events i n the ?on source? register. 4. sleep transitions are not possible when any of the battery c harger interrupts is set. if any of the battery charger interrup ts is asserted when a sleep transition is requested, then the transit ion will be unsuccessful and the WM8310 will remain in the on power state. see section 17.7.8 for details of the battery charger interrupts. 5. sleep events are not recorded in the ?off source? register. 11.4 power state interrupts power state transitions are associated with a num ber of interrupt event flags. transitions to backup, sleep, on or off states are indicated by the interrupt bits described in table 4. each of these secondary interrupts triggers a primary powe r state interrupt, ps_int (see section 23). this can be masked by setting the mask bit(s) as described in table 4. address bit label description r16402 (4012h) interrupt status 2 2 ps_por_eint power on reset interrupt (rising edge triggered) note: cleared when a ?1? is written. 1 ps_sleep_off_eint sleep or off interrupt (power state transition to sleep or off states) (rising edge triggered) note: cleared when a ?1? is written. 0 ps_on_wake_eint on or wake interrupt (power state transition to on state) (rising edge triggered) note: cleared when a ?1? is written. r16410 (401ah) interrupt status 2 mask 2 im_ps_por_eint interrupt mask. 0 = do not mask interrupt. 1 = mask interrupt. default value is 1 (masked) 1 im_ps_sleep_off_eint interrupt mask. 0 = do not mask interrupt. 1 = mask interrupt. default value is 1 (masked) 0 im_ps_on_wake_eint interrupt mask. 0 = do not mask interrupt. 1 = mask interrupt. default value is 1 (masked) table 4 power state interrupts 11.5 power state gpio indication the WM8310 can be configured to generate logic signals vi a gpio pins to indicate the current power state. see section 21 for details of configuring gpio pins. a gpio pin configured as ?on state? output will be asserted when the WM8310 is in the on state. a gpio pin configured as ?sleep state? output will be asserted when the WM8310 is in the sleep state.
WM8310 pre-production w pp, may 2012, rev 3.1 38 11.6 on pin function the on pin is intended for connection to the master pow er switch on the user?s application. it can be used to start-up the WM8310 from the sleep or o ff states and also to power down the system. this pin operates on the ldo12 (vpmic) power domai n and has an internal pull-up resistor. this pin is asserted by shorting it to gnd. a de-bounc e circuit is provided on this input pin. the behaviour of the on pin is programmable. the primary action taken on asserting this pin is determined by the on_pin_primact register field. note that the on_pin_int interrupt event is always raised when the on pin is asserted. if the pin is held asserted for longer than the ti meout period set by on_pin_to, then a secondary action is executed. the secondar y action is determined by the on _pin_secact register field. if the pin is held asserted for a further timeout period, then a tertiary action is executed. the tertiary action is not programmable, and is to generate an off request. an off request initiated by the on pin may be masked during battery charging when the chg_off_mask bit is set. this allows user-initiated off events to be disabled in order to maintain the battery charger operation. see section 17.7.2. the status of the on pin can be read at any time via the on_pin_sts register. note that the on pin control registers are locked by t he WM8310 user key. these registers can only be changed by writing the appropriate code to the secu rity register, as described in section 12.4. address bit label default description r16389 (4005h) on pin control 9:8 on_pin_secact 01 secondary action of on pin (taken after 1 timeout period) 00 = interrupt 01 = on request 10 = off request 11 = reserved protected by user key 5:4 on_pin_primact 00 primary action of on pin 00 = ignore 01 = on request 10 = off request 11 = reserved note that an interrupt is always raised. protected by user key 3 on_pin_sts 0 current status of on pin 0 = asserted (logic 0) 1 = not asserted (logic 1) 1:0 on_pin_to 00 on pin timeout period 00 = 1s 01 = 2s 10 = 4s 11 = 8s protected by user key table 5 on pin control registers the on pin interrupt event is always raised as part of the primary action when the on pin is asserted. the on pin interrupt is a selectable opt ion as the secondary action. the on pin interrupt event is also raised when the on pin is de-asserted. the on pin interrupt event is indicated by the on_p in_cint register field. this secondary interrupt triggers a primary on pin interrupt, on_pin_int (see section 23). this can be masked by setting the mask bit as described in table 6.
pre-production WM8310 w pp, may 2012, rev 3.1 39 address bit label description r16401 (4011h) interrupt status 1 12 on_pin_cint on pin interrupt. (rising and falling edge triggered) note: cleared when a ?1? is written. r16409 (4019h) interrupt status 1 mask 12 im_on_pin_cint interrupt mask. 0 = do not mask interrupt. 1 = mask interrupt. default value is 1 (masked) table 6 on pin interrupt 11.7 reset pin function the reset pin is an active low input/output which is used to command hardware resets in the WM8310 and in other connected devices. the pin is an open-drain type, with integrated pull-up; it can be driven low by external sources or by the WM8310 itself. the WM8310 drives the reset pin low in the off state. the output status of the reset pin in sleep is configurable; this is determined by the rst_slpena register bit as defined in table 7. the WM8310 clears the reset pin following the transition to on. on completion of the state transition, the reset pin is held low for a further del ay time period, extending the reset low duration. the reset delay period is set by the rst_dur register bit. see figure 6 for further details. the WM8310 detects a hardware reset request whenever the reset pin is driven low by an external source. in this event, the WM8310 resets t he internal control registers (excluding the rtc) and initiates a start-up sequence. see section 24. it is possible to mask the reset pin input in the sl eep state by setting the rst_slp_msk register bit. in sleep mode, if rst_slp_msk is set, the WM8310 will take no action if the reset pin is pulled low. note that the reset pin control registers are locked by the WM8310 user key. these registers can only be changed by writing the appropriate code to the se curity register, as described in section 12.4. address bit label default description r16390 (4006h) reset control 5 rst_slp_msk 1 masks the reset pin input in sleep mode 0 = external reset active in sleep 1 = external reset masked in sleep protected by user key 4 rst_slpena 1 sets the output status of reset pin in sleep 0 = reset high (not asserted) 1 = reset low (asserted) protected by user key 1:0 rst_dur 11 delay period for releasing reset after on or wake sequence 00 = 3ms 01 = 11ms 10 = 51ms 11 = 101ms protected by user key table 7 reset pin control registers
WM8310 pre-production w pp, may 2012, rev 3.1 40 the WM8310 can generate an auxiliary reset output via a gpio pin configured as ?auxiliary reset? output (see section 21). this signal is asserted in the off state. the status of the auxiliary reset in the sleep state is configurable, using the auxrst_slpena register bit as defined in table 8. address bit label default description r16390 (4006h) reset control 6 auxrst_slpe na 1 sets the output status of auxiliary reset (gpio) function in sleep 0 = auxiliary reset not asserted 1 = auxiliary reset asserted protected by user key table 8 auxiliary reset (gpio) control the timing details of the reset pin relative to an on state tr ansition are illustrated in figure 6. figure 6 reset pin output
pre-production WM8310 w pp, may 2012, rev 3.1 41 12 control interface 12.1 general description the WM8310 is controlled by writing to its control r egisters. readback is available for all registers, including chip id, power management status and gpio status. the control interface can operate as a 2-wire (i2c) or 4-wire (spi) control interface. readback is provided on the bi -directional pin sda1 in 2-wire (i2c) mode. the WM8310 control interface is powered by the dbvdd power domain. the control interface mode is determined by the logi c level on the cifmode pin as shown in table 9. cifmode interface format low 2-wire (i2c) mode high 4-wire (spi) mode table 9 control interface mode selection 12.2 2-wire (i2c) control mode in 2-wire (i2c) mode, the WM8310 is a slave device on the control interface; sclk1 is a clock input, while sda1 is a bi-directional data pin. to allow arbitration of multiple slaves (and/or multiple masters) on the same interface, the WM8310 transmits logic 1 by tri-stating the sda1 pin, rather than pulling it high. an external pull-up re sistor is required to pull the sda1 line high so that the logic 1 can be recognised by the master. in order to allow many devices to share a singl e 2-wire control bus, ever y device on the bus has a unique 8-bit device id (this is not the same as the 16-bit address of each register in the WM8310). the device id is determined by the logic level on the cs pin as shown in table 10. the lsb of the device id is the read/write bit; this bit is se t to logic 1 for ?read? and logic 0 for ?write?. cs device id low 0110 100x = 68h(write) / 69h(read) high 0110 110x = 6ch(write) / 6dh(read) table 10 control interface device id selection the WM8310 operates as a slave device only. the controller indicates the start of data transfer with a high to low transition on sda1 while sclk1 remains high. this indicates that a device id, register address and data will follow. the WM8310 responds to t he start condition and shifts in the next eight bits on sda1 (8-bit device id including read/write bit, msb first). if the dev ice id received matches the device id of the WM8310, then the WM8310 responds by pulling sda1 low on the next clock pulse (ack). if the device id is not recognised or the r/w bit is set incorrectly, the WM8310 returns to the idle condition and waits for a new start condition and valid address. if the device id matches the device id of the WM8310, the data transfer continues as described below. the controller indicates the end of data trans fer with a low to high transition on sda1 while sclk1 remains high. after receiving a complete address and data sequence the WM8310 returns to the idle state and waits for another start condition. if a start or stop condition is detected out of sequence at any point during data transfer (i.e. sda1 changes while sclk1 is high), the device returns to the idle condition. the WM8310 supports the following read and write operations: ? single write ? single read ? multiple write using auto-increment ? multiple read using auto-increment the sequence of signals associated with a single regi ster write operation is illustrated in figure 7.
WM8310 pre-production w pp, may 2012, rev 3.1 42 figure 7 control interface 2-wire (i2c) register write the sequence of signals associated with a single regi ster read operation is illustrated in figure 8. figure 8 control interface 2-wire (i2c) register read the control interface also supports other register operations, as listed above. the interface protocol for these operations is summarised below. the terminology used in the following figures is detailed in table 11. note that, for multiple write and multiple read operations, the auto-increment option must be enabled. this feature is enabled by default; it is described in table 12 below. terminology description s start condition sr repeated start a acknowledge (sda low) a not acknowledge (sda high) p stop condition r/w readnotwrite 0 = write 1 = read [white field] data flow from bus master to WM8310 [grey field] data flow from WM8310 to bus master table 11 control interface terminology figure 9 single register write to specified address
pre-production WM8310 w pp, may 2012, rev 3.1 43 figure 10 single register read from specified address figure 11 multiple register write to specified address using auto-increment figure 12 multiple register read from specified address using auto-increment figure 13 multiple register read from last address using auto-increment multiple write and multiple read operations enable the host processor to access sequential blocks of the data in the WM8310 register map faster than is possible with single register operations. the auto- increment option is enabled when the autoinc register bit is set. this bit is defined in table 12. auto-increment is enabled by default. address bit label default description r16391 (4007h) control interface 2 autoinc 1 enable auto-increment function 0 = disabled 1 = enabled table 12 auto-increment control
WM8310 pre-production w pp, may 2012, rev 3.1 44 12.3 4-wire (spi) control mode in this mode, the WM8310 registers are accessed us ing a 4-wire serial control interface. the cs and sclk1 pins provide the ?chip select? and ?serial data clock? functions respec tively. serial data input is supported on the sda1 pin; serial dat a output is supported on the sdout1 pin. a control word consists of 32 bits . the first bit is the read/write bi t (r/w), which is followed by 15 address bits (a14 to a0) that determine which contro l register is accessed. the remaining 16 bits (b15 to b0) are data bits, corresponding to the 16 bits in each control register. in write operations (r/w=0), all sda1 bits are driven by the controlling device. each rising edge of sclk1 clocks in one data bit from the sda1 pin. a rising edge on cs latches in a complete control word consisting of the last 32 bits. in read operations, the sda1 pin is ignored following receipt of the valid register address. the data bits are output by the WM8310 on the sdout1 pi n. sdout1 is undriven (high impedance) when not outputting register data bits. the sdout1 pin is an open drain output; an exter nal pull-up resistor to dbvdd is required on sdout1 in 4-wire (spi) mode. the sequence of signals associated with a register write operation is illustrated in figure 14. r/w a14 a13 a12 a2 a1 sdin sclk cs 15-bit control register address 16-bit control register data a0 b15 b14 b13 b2 b0 b1 figure 14 control interface 4-wire (spi) register write the sequence of signals associated with a regist er read operation is illustrated in figure 15. figure 15 control interface 4-wire (spi) register read 12.4 register locking selected registers are protected by a security ke y. these registers can only be written to when the appropriate ?unlock? code has been writt en to the security key register. the protected registers include those associated wi th reset control, otp programming, rtc trim and battery charger operation. other selected functions also include protected registers; the affected registers are identified in the register map definitions throughout the document, and also in section 29. to unlock the protected registers, a value of 9716h must be written to the security register (r16392), as defined in table 13.
pre-production WM8310 w pp, may 2012, rev 3.1 45 it is recommended to re-lock the protected registers immediately after writing to them. this helps protect the system against accidental overwriting of r egister values. to lock the protected registers, a value of 0000h should be written to the security register. address bit label default description r16392 (4008h) security key 15:0 security [15:0] 0000h security key a value of 9716h must be written to this register to access the user- keyed registers. table 13 security key register 12.5 software reset and chip id a software reset can be commanded by writing to regi ster 0000h. this is a read-only register field and the contents of this register will not be affected by a write operation. for more details of the different reset types, see section 24. note that a maximum of 6 software resets is permitted. if more than 6 software resets are scheduled, the WM8310 will remain in the off state until the next valid on state transition event occurs. the chip id can be read back from register 0000h. other id fields can be read from the registers defined in table 14. address bit label default description r0 (0000h) reset/id 15:0 chip_id [15:0] 0000h writing to this register causes a software reset. the register map contents may be reset, depending on sw_reset_cfg. reading from this register will indicate chip id. r1 (0001h) revision 15:8 parent_re v [7:0] 00h the revision number of the parent die 7:0 child_rev [7:0] 00h the revision number of the child die (when present) r16384 (4000h) parent id 15:0 parent_id [15:0] 6204h the id of the parent die table 14 reading device information 12.6 software scratch register the WM8310 provides one 16-bit register as a ?software scratch? regist er. this is available for use by the host processor to store data for any purpose required by the application. the contents of the software scratch register are retained in the backup power state. address bit label default description r16393 (4009h) software scratch 15:0 sw_scratc h [15:0] 0000h software scratch register for use by the host processor. note that this register?s contents are retained in the backup power state. table 15 software scratch register
WM8310 pre-production w pp, may 2012, rev 3.1 46 13 clocking and os cillator control 13.1 general description the WM8310 incorporates a 32.768khz crystal oscillato r in order to maintain the real time clock (rtc). an external crystal is nor mally required. alternatively, a 32. 768khz signal may be input directly on the xti pin. the crystal oscillator and rtc ar e normally enabled at all times, including the off and backup power states. it is possible to disable the crystal oscillator in backup for power-saving rtc ?unclocked? mode if desired. the WM8310 cl ock functions are illustrated in figure 16. figure 16 clocking configuration the 32.768khz crystal oscillator is enabled using the xtal_ena register. the crystal oscillator is enabled in the off, on and sleep states when xtal_ena is set. the status of the crystal oscillator in backup is selected using the xtal_bkupena register. note that the xtal_ena field is set via otp/ice settings only; it cannot be changed by writing to the control register. also, if an external 32.768khz signal is connected as an input to the xti pin, and the crystal is omitted, it is still required to set xtal_ena = 1 for normal operation. the crystal oscillator can be disabled in the backup state by setting the xtal_bkupena register bit to 0. this feature may be used to minimise the device power consumption in the backup state, as described in section 20.5. the crystal oscilla tor is maintained in the backup state if both xtal_ena and xtal_bkupena are set to 1. a clock output signal clkout is provided, for the purpose of clocking other devices. this output may be driven by the 32.768khz oscillator or by t he output of a frequency locked loop (fll). the fll provides a flexible capability to generate a new clo ck signal either from the 32.768khz oscillator or from an external input clkin. the fll is toler ant of jitter and may be used to generate a stable clock signal from a less stable input reference. the fll output can be routed to the clkout pin. the clkout signal can be enabled or disabled directly by writing to the clkout_ena register in the on or sleep power states. the clkout can also be controlled as part of the power state transitions using the clkout_slo t and clkout_slp_slot register fields. see section 11.3 for a description of the state transition timeslots. the clkout pin may be configured as a cmos output or as an open-drain output. at high frequencies, the cmos output is recommended. the clkout signal is referenced to the dbvdd power domain. if the xtal_inh bit is set, then an ?on? state trans ition is delayed until the clkout output is valid. (note that clkout may be the crystal oscillator output, or may be the fll output.) this may be desirable if the clkout signal is used as a clo ck for another circuit, to ensure that the clkout signal has been verified before the ?on? state transit ion occurs. note that the clkout output is always disabled in the off power state; it is ty pically enabled as part of the ?on? state transition sequence. setting xtal_inh = 1 ensures that the clkout output cannot be enabled until the source signal (crystal oscilla tor or fll) has been verified. the clkout control fields are described in table 16. some of these controls may also be stored in the integrated otp memory. see section 14 for details.
pre-production WM8310 w pp, may 2012, rev 3.1 47 the 32.768khz oscillator may also be output on a gpio pin, as described in section 21. note that a gpio pin configured as 32.768khz out put will continue to output the oscillator clock in the off power state; this may be used to provide clocking to t he processor in the off state, provided that the selected power domain for that gpio pin remains enabled in the off state. the clkout output is always disabled in the off power state. a separate internal rc oscillator generates the r equired clocks for the integrated dc-dc converters on the WM8310. note that a 2mhz ?external power cl ock?, derived from this oscillator, may be output on a gpio pin to provide synchr onised clocking of external dc- dc converters if required (see section 21). the 2mhz external power clock is only enabled when either of the external power enable signals epe1 or epe2 is asserted. the exte rnal power enable (epe) signals are controlled as described in section 15.3. note that the clkout_ena control register is locked by the WM8310 user key. this register can only be changed by writing the appropriate code to the se curity register, as described in section 12.4. address bit label default description r16528 (4090h) clock control 1 15 clkout_en a 0 clkout output enable 0 = disabled 1 = enabled protected by user key 13 clkout_od 0 clkout pin configuration 0 = cmos 1 = open drain 10:8 clkout_slo t 000 clkout output enable on slot select 000 = do not enable 001 = enable in timeslot 1 010 = enable in timeslot 2 011 = enable in timeslot 3 100 = enable in timeslot 4 101 = enable in timeslot 5 110 = do not enable 111 = do not enable 6:4 clkout_slp slot 000 clkout output sleep slot select 000 = controlled by clkout_ena 001 = disable in timeslot 5 010 = disable in timeslot 4 011 = disable in timeslot 3 100 = disable in timeslot 2 101 = disable in timeslot 1 110 = controlled by clkout_ena 111 = controlled by clkout_ena 0 clkout_sr c 0 clkout output source select 0 = fll output 1 = 32.768khz oscillator r16529 (4091h) clock control 2 15 xtal_inh 0 crystal start-up inhibit 0 = disabled 1 = enabled when xtal_inh=1, the ?on? transition is inhibited until the crystal oscillator is valid 13 xtal_ena 0 crystal oscillator enable 0 = disabled at all times 1 = enabled in off, on and sleep states (note that the backup behaviour is determined by xtal_bkupena.)
WM8310 pre-production w pp, may 2012, rev 3.1 48 address bit label default description 12 xtal_bkupe na 1 selects the rtc and 32.768khz oscillator in backup state 0 = rtc unclocked in backup 1 = rtc maintained in backup (note that xtal_ena must also be set if the rtc is to be maintained in backup.) table 16 clocking control 13.2 crystal oscillator the crystal oscillator generates a 32.768khz referenc e clock, which is used to provide reference clock for the real time clock (rtc) in the WM8310. it may also be used as a reference input to the fll, for the purpose of generating other clocks. the oscillator requires an external crystal on the xti and xto pins, as well as two capacitor s, connected as shown in figure 17. figure 17 crystal oscillator a suitable crystal oscillator should be selected in accordance with the following requirements: parameter min max units nominal frequency 32.768 khz series resistance 50 70 k ? maximum driving level 0.5 ? w table 17 selection of crystal oscillator component the load capacitors c1 and c2 should be selected according to the recommended load capacitance, c l of the crystal, which is given by the following equation: assuming c1 = c2 and c stray = 2.75pf (typical pad i/o capacitance), then: c1 = c2 = 2 x (c l - 2.75pf). for example, if the crystal has a load capacitance c l = 9pf, then c1 = c2 = 12.5pf.
pre-production WM8310 w pp, may 2012, rev 3.1 49 if a suitable 32.768khz clock is already present el sewhere in the system, it is possible for the WM8310 to use that external clock instead. the ex ternal clock should be applied to pin xti, and the xto pin left floating in this case. 13.3 frequency locked loop (fll) the integrated fll can be used to generate a clo ck on the clkout pin from a wide variety of different reference sources and frequencies. the fll can use either clkin or the 32.768khz oscillator as its reference. a wide range of cl kin frequencies can be supported; this may be a high frequency (eg. 12.288mhz) or low frequency (eg. 32.768khz ) reference. the fll is tolerant of jitter and may be used to generate a stable clock refer ence from a less stable input signal. the fll characteristics are summarised in ?electrical characteristics?. to simplify the configuration of the fll, an ?aut omatic? mode is provided in order to synthesize a number of commonly used reference frequencies us ing the 32.768khz crystal oscillator as a reference. the fll is enabled using the fll_ena register bi t. note that, when changing fll settings, it is recommended that the digital circ uit be disabled via fll_ena and then re-enabled after the other register settings have been updated. when changing the input reference frequency f ref , it is recommended that the fll be reset by setting fll_ena to 0. note that, when fll_ena = 0, the readback value of all the fll configuration registers (r16530 through to r16534) is not valid. it is still possible to write to the registers as normal, but the correct values will not read back until the fll is enabled by setting fll_ena to 1. the fll input reference is conf igured using the fll_clk_src regist er bit. the available sources are the clkin pin or the 32.768khz crystal oscillator. the field fll_clk_ref_div provides the option to divide the selected input reference by 1, 2, 4 or 8. this field should be set to br ing the reference down to 13.5mhz or below. for best performance, it is recommended that the highest possible frequency - wi thin the 13.5mhz limit - should be selected. the field fll_ctrl_rate controls in ternal functions within the fll; it is recommended that only the default setting be used for this parameter. fll_gain controls the internal loop gain and should be set to the recommended value quoted in table 20. the fll output frequency is directly determined from fll_fratio, fll_outdiv and the real number represented by fll_n and fll_k. the field fll_n is an integer (lsb = 1); fll_k is the fractional portion of the number (msb = 0.5). the fractional portion is only valid when enabled by the field fll_frac. power consumption in the fll is reduced in in teger mode; however, the performance may also be reduced, with increased noise or jitter on the output. if low power consumption is required, then fll setti ngs must be chosen where n.k is an integer (ie. fll_k = 0). in this case, the fractional mode can be disabled by setting fll_frac = 0. for best fll performance, a non-integer value of n.k is required. in this case, the fractional mode must be enabled by setting fll_frac = 1. the fll settings must be adjusted, if necessary, to produce a non-integer value of n.k.
WM8310 pre-production w pp, may 2012, rev 3.1 50 the fll output frequency is generated according to the following equation: f out = (f vco / fll_outdiv) the fll operating frequency, f vco is set according to the following equation: f vco = (f ref x n.k x fll_fratio) see table 20 for the coding of t he fll_outdiv and fll_fratio fields. f ref is the input frequency, as determined by fll_clk_ref_div. f vco must be in the range 90-100 mhz. frequencies outside this range cannot be supported. note that the output frequencies that do not lie within the ranges quoted above cannot be guaranteed across the full range of device operating temperatures. in order to follow the above requirements for f vco , the value of fll_outdiv should be selected according to the desired output f out . the divider, fll_outdiv, must be set so that f vco is in the range 90-100mhz. the available divi sions are integers from 4 to 64. some typical settings of fll_outdiv are noted in table 18. output frequency f out fll_outdiv 2.8125 mhz - 3.125 mhz 011111 (divide by 32) 3.75 mhz - 4.1667 mhz 010111 (divide by 24) 5.625 mhz - 6.25 mhz 001111 (divide by 16) 11.25 mhz - 12.5 mhz 000111 (divide by 8) 18 mhz - 20 mhz 000100 (divide by 5) 22.5 mhz - 25 mhz 000011 (divide by 4) table 18 selection of fll_outdiv the value of fll_fratio should be selected as described in table 19. reference frequency f ref fll_fratio 1mhz - 13.5mhz 000 (divide by 1) 256khz - 1mhz 001 (divide by 2) 128khz - 256khz 010 (divide by 4) 64khz - 128khz 011 (divide by 8) less than 64khz 100 (divide by 16) table 19 selection of fll_fratio in order to determine the remaining fll parameters, the fll operating frequency, f vco , must be calculated, as given by the following equation: f vco = (f out x fll_outdiv) the value of fll_n and fll_k can then be determined as follows: n.k = f vco / (fll_fratio x f ref ) see table 20 for the coding of t he fll_outdiv and fll_fratio fields. note that f ref is the input frequency, after division by fll_clk_ref_div, where applicable.
pre-production WM8310 w pp, may 2012, rev 3.1 51 in fll fractional mode, the fractional portion of the n.k multiplier is held in the fll_k register field. this field is coded as a fixed poi nt quantity, where the msb has a weighting of 0.5. note that, if desired, the value of this field may be calculated by multiplying k by 2^16 and treating fll_k as an integer value, as illustrated in the following example: if n.k = 8.192, then k = 0.192. multiplying k by 2^16 gives 0.192 x 65536 = 12582.912 (decimal) = 3126 (hex). for best fll performance, the fll fractional mode is recommended. therefore, if the calculations yield an integer value of n.k, then it is recomm ended to adjust fll_outdiv in order that n.k is a non-integer value. care must always be taken to ensure that the fll operating frequency, f vco , is within its recommended limits of 90-100 mhz. the register fields that control the fll are described in table 20. address bit label default description r16530 (4092h) fll control 1 2 fll_frac 0 fractional enable 0 = integer mode 1 = fractional mode integer mode offers reduced power consumption. fractional mode offers best fll performance, provided also that n.k is a non- integer value. 0 fll_ena 0 fll enable 0 = disabled 1 = enabled note - this bit is reset to 0 when the off power state is entered. r16531 (4093h) fll control 2 13:8 fll_outdiv [5:0] 000000 f out clock divider 000000 = reserved 000001 = reserved 000010 = reserved 000011 = 4 000100 = 5 000101 = 6 ? 111110 = 63 111111 = 64 (f out = f vco / fll_outdiv) 6:4 fll_ctrl_r ate [2:0] 000 frequency of the fll control block 000 = f vco / 1 (recommended value) 001 = f vco / 2 010 = f vco / 3 011 = f vco / 4 100 = f vco / 5 101 = f vco / 6 110 = f vco / 7 111 = f vco / 8 recommended that this register is not changed from default. 2:0 fll_fratio [2:0] 000 f vco clock divider 000 = 1 001 = 2
WM8310 pre-production w pp, may 2012, rev 3.1 52 address bit label default description 010 = 4 011 = 8 1xx = 16 000 recommended for high f ref 011 recommended for low f ref r16532 (4094h) fll control 3 15:0 fll_k [15:0] 0000h fractional multiply for f ref (msb = 0.5) r16533 (4095h) fll control 4 14:5 fll_n [9:0] 177h integer multiply for f ref (lsb = 1) 3:0 fll_gain [3:0] 0000 gain applied to error 0000 = x 1 (recommended value) 0001 = x 2 0010 = x 4 0011 = x 8 0100 = x 16 0101 = x 32 0110 = x 64 0111 = x 128 1xxx = x 256 recommended that this register is not changed from default. r16534 (4096h) fll control 5 4:3 fll_clk_re f_div [1:0] 00 fll clock reference divider 00 = 1 01 = 2 10 = 4 11 = 8 clkin must be divided down to <=13.5mhz. for lower power operation, the reference clock can be divided down further if desired. 1:0 fll_clk_sr c [1:0] 00 fll clock source 00 = 32.768khz xtal oscillator 01 = clkin 10 = reserved 11 = reserved table 20 fll control
pre-production WM8310 w pp, may 2012, rev 3.1 53 13.3.1 fll auto mode to simplify the configuration of the fll, an ?aut omatic? mode is provided in order to synthesize a number of commonly used reference frequencies us ing the 32.768khz crystal oscillator as a reference. fll automatic mode is selected by setting the f ll_auto register bit as described in table 21. when fll_auto is set, the fll is automatically conf igured to select the 32.768khz oscillator as the fll reference, and will generate the output frequency selected by fll_auto_freq. fll automatic mode should be selected while the f ll is disabled (fll_ena = 0). after automatic mode has been selected, the fll can be enabled and disabled using fll_ena, as described in table 20. address bit label default description r16529 (4091h) clock control 2 7 fll_auto 1 fll automatic mode enable 0 = manual configuration mode 1 = automatic configuration mode (to enable the fll output, fll_ena must also be set in automatic mode) 2:0 fll_auto_f req [2:0] 000 fll automatic mode frequency select 000 = 2.048mhz 001 = 11.2896mhz 010 = 12mhz 011 = 12.288mhz 100 = 19.2mhz 101 = 22.5792mhz 110 = 24mhz 111 = 24.576mhz table 21 fll automatic mode
WM8310 pre-production w pp, may 2012, rev 3.1 54 14 instantconfig? (ice) and otp memory control 14.1 general description the WM8310 is a highly configurable device which can be tailored specif ically to the requirements of a complex system application. the sequencing and voltage control of the integrated dc-dc converters and ldos in power-up, shut-down and sl eep conditions is crucial to the robust operation of the application. in development, the WM8310 allows designers to modify or experiment with different settings of the control sequences by writing to the applicable regist ers in the off state prior to commanding an ?on? state transition. configuration settings can also be stored on an external eeprom and loaded onto the WM8310 as required, using the instantconfig? eeprom (ice) interface. for production use, the WM8310 provides an on-chip a one-time programmable (otp) memory, in which the essential parameters for starting up t he device can be programmed. this allows the WM8310 to start up and shut down the system with no dependency on any other devices for application-specific conf iguration parameters. 14.2 ice and otp memory definition an illustration of the WM8310 memory locations is s hown in figure 18. the main register map of the WM8310 contains a block of data in a ?window? ar ea which is mirrored in the otp and/or the ice memory. data from the external ice memory can be loaded into the window area. data can be transferred from the window into otp memory and also from the otp memory into the window. the window is called the device configuration regist er window (dcrw); the data in this window is mirrored in other locations within the WM8310 register map. register map 00h 08h instantconfig? eeprom (ice) memory otp page3 data otp page 2 data otp page 1 data otp memory otp page 0 data 00h 08h dcrw page 4 data dcrw page 2 data dcrw page 1 data dcrw page 0 data 10h 18h ice page 3 data power management & configuration registers WM8310 dcrw page 3 data 10h factory set data unique id user configurable key ice check ice page 2 data ice page 4 data 18h 20h 28h note that the recommended external ice memory is arranged in 8-bit words figure 18 ice and otp memory layout
pre-production WM8310 w pp, may 2012, rev 3.1 55 the dcrw contains 5 pages of data, as illustrated in figure 18. page 0 of the dcrw contains a 128-bit pseudo-random unique id. the unique id is written to the otp at the time of manufacture. it is copi ed to the dcrw when the WM8310 schedules an ?on? transition. this data cannot be changed. page 1 of the dcrw contains factory-set calibration and configuration data. this data is written to the otp at the time of manufacture. it is copi ed to the dcrw when the WM8310 schedules an ?on? transition. this data cannot be changed. page 2 and page 3 of the dcrw contain bootstrap c onfiguration data. this defines the sequence and voltage requirements for powering up the WM8310, and for configuring functions such as the clocks, fll, gpio1-6 and led status indicators . under default conditions, the bootstrap data is loaded into the dcrw when the WM8310 schedules an ?on? transition. the WM8310 automatically determines whether to load the bootstrap data from ice or from otp as described in section 14.3. page 4 of the dcrw contains a register that is used for ice validity checking. it is copied to the dcrw whenever the bootstrap configuration data is loaded from ice in response to a start-up request in development mode. this register fiel d enables the ice data to be checked for valid content. the otp contains 4 pages of data, as illustrat ed in figure 18. the contents of the otp pages correspond to pages 0, 1, 2 and 3 of the dcrw register map addresses. the ice memory contains 3 pages of data, as illust rated in figure 18. the contents of the ice pages correspond to pages 2, 3 and 4 of the dcrw register map addresses. note that the ice memory (recommended component) is arranged as 8-bit words in ?big-endian? format, and is therefore addressed as 6 pages of 8- bit data, corresponding to 3 pages of 16-bit data. for example, the ice memory address 00h corresponds to bits 15:8 of the first register map word in dcrw page 2, and ice address 01h corresponds to bits 7:0 of that same register word in dcrw. the dcrw can be accessed directly using the cont rol interface in the off, on and sleep power states. note that read/write access to the ice or otp memories is not possible directly; these can only be accessed by copying to/from the dcrw. in the program state, page 2 and page 3 of the dcrw can be permanently written to the otp. 14.3 bootstrap (start-up) function under default conditions, the WM8310 bootstrap configuration data is loaded when the WM8310 schedules an ?on? transition. the bootstrap confi guration data is loaded into page 2 and page 3 of the dcrw from either an external ice or from t he integrated otp. (the factory-set data in page 0 and page 1 is always loaded from the integrated otp memory.) if development mode is selected, then the bootstrap data is loaded from the instantconfig? eeprom (ice). if development mode is not selected, then the bootstrap data is loaded from the otp memory. 14.3.1 start-up from otp memory in volume production, development mode is not us ually selected. in this case, the bootstrap configuration data is loaded from the internal otp memory. the WM8310 performs a check for valid otp data; if the otp_cust_id field is set to zero, then the WM8310 remains in the off power state. a non-zero otp_cust_id field is used to confirm valid otp contents. the otp memory contents are defined similarly to pages 0, 1, 2 and 3 of the dcrw memory contents listed in section 14.6.
WM8310 pre-production w pp, may 2012, rev 3.1 56 14.3.2 start-up from ice memory (development mode) development mode is selected if a logic high le vel (referenced to the ldo12 vpmic voltage) is present on sclk2. this should be implemented us ing a pull-up resistor. see section 14.3.4 for details of the external ice memory connection. if development mode is selected, then the WM8310 performs a check for valid ice data; if the ice is not connected or contains invalid data, then the WM8310 remains in the off power state. the ice data is deemed valid is the ice_valid_d ata field contains the value a596h. the WM8310 also performs a check for valid cont ents in the otp_cust_id field in development mode; if the otp_cust_id field is set to zero, then the WM8310 remains in the off power state. a non-zero otp_cust_id field is used to confirm valid ice contents. note that, if a gpio pin is configured in ice memory as ?power on/off request? (gpn_fn=02h), then inverted (active low) polarity should be selected for that gpio (gpn_pol=0). the non-inverted (active high) polarity cannot be fully support ed for this function in development mode. this restriction is only applicabl e in development mode, and applies only to the gpio ?power on/off request? function. see section 21 for details of the gpio pin configuration registers. the non-inverted (active high) polarity can be support ed for the gpio ?power on/off request? function in development mode if the corresponding gpn_pol regist er bit in the otp memory is set to 1. note that, if the otp memory is unprogrammed, the gpn_pol bits will default to 0. 14.3.3 start-up from dcrw register settings under default settings, the bootstrap configuration data is always loaded when an on transition is scheduled. for development purposes , this can be disabled by cl earing the reconfig_at_on register bit. (note that reconfig_at_on only se lects whether page 2/3/4 data is loaded; page 0/1 data is always loaded from otp whenev er an on transition is scheduled.) when reconfig_at_on = 1, the bootstrap data is reloaded from either the ice or otp when an on transition is scheduled. the logic level on sclk2 is checked to determine whether the ice or the otp memory should be used. if reconfig_at_on = 0, then the latest contents of the dcrw are used to configure the start-up sequence. note that, when WM8310 start-up is scheduled using th is method, the contents of otp_cust_id is still checked for valid contents. in development m ode, the ice_valid_data field is also checked. see section 14.3.2 for details. note that the reconfig_at_on control register is locked by the WM8310 user key. this register can only be changed by writing the appropriate code to the security register, as described in section 12.4. address bit label default description r16390 (4006h) reset control 15 reconfig_a t_on 1 selects if the bootstrap configuration data should be reloaded when an on transition is scheduled 0 = disabled 1 = enabled protected by user key table 22 bootstrap configuration reload control 14.3.4 external ice memory connection the recommended component for the external ice is the microchip 24aa32a, which provides 32 bytes of memory space. the ice interfaces with the WM8310 via the sclk2 and sda2 pins, and initiates an i2c transfer of data from the ice when required. the necessary el ectrical connections for this device are illustrated in figure 19. the WM8310 assumes an eeprom device id of 1010 0001 (a1h) for ice read cycles. the ice memory contents are defined similarly to pages 2, 3 and 4 of the dcrw memory contents defined in section 14.6.
pre-production WM8310 w pp, may 2012, rev 3.1 57 figure 19 ice memory connection note that the WM8310 does not support programming the external ice memory. external programming of ice whilst physically c onnected to the WM8310 is possible by putting the WM8310 in the off state. this is supported on t he evaluation board, provided the voltage levels on sclk2 and sda2 are less than or equal to the ldo 12 vpmic voltage. note that the write-protect (wp) pin on the ice must be connected to gnd (vss) in this case. 14.4 otp / ice memory control the otp and ice memory commands are initiated by writing to the otp control register, as defined in section 14.4.6. the supported commands are described below. read ice memory - this command instructs the WM8310 to load data from the external ice into the WM8310 dcrw memory area. note that this command is performed automatically when the WM8310 starts up in development mode. read otp memory - this command instructs the WM8310 to load data from the integrated otp memory area into the WM8310 dcrw memory area. note that this command is performed automatically when the WM8310 starts up in normal (ie. non-development) mode. write otp memory - this command instructs the WM8310 to program the integrated otp, by writing a copy of the dcrw memory area (pages 0, 1, 2 and 3) to the otp memory. this command should be performed after the required settings have been configured in the dcrw memory. the required settings can be configured in the dcrw either as a result of a ice read command, or else through register writes in the program power st ate. note that the write otp command should only be performed once on each otp page; after the write otp command has been performed, the contents of the affected page(s) cannot be erased or re-programmed. verify otp memory - this command instructs the WM8310 to compare the contents of the otp memory with the contents of the dcrw memory. the verify otp command performs a check that the otp data is identical to the dcrw contents, in order to confirm the success of the write otp operation. for increased reliability, the WM8310 c an apply a ?margin read? function when verifying the otp memory; it is recommended that the margin read option is used, as described in section 14.4.4. finalise otp pages - this command instructs the WM8310 to set the otp_cust_final bit in the otp memory. the finalise otp command ensur es that any subsequent otp_write commands to page 2 or page 3 of the otp will have no effect and that the otp contents are maintained securely.
WM8310 pre-production w pp, may 2012, rev 3.1 58 the otp and ice memory commands are each described in the following sections. note that, in some cases, commands may be executed on a single page of memory or may be executed as a bulk operation on all available memory pages. completion of each otp or ice memory command is indicated via an interrupt flag, as described in section 14.5. the pass/fail outcome of any verify otp command is also indicated by the interrupt bits. note that read/write access to the WM8310 register map is not supported while a ice/otp command is in progress. it is recommended that the irq pin is configured to indicate any ice/otp interrupt event; the host processor should read the otp/ice interrupt event flags to confirm the otp/ice command status following the assertion of the irq pin. the programming supply voltage progvdd is requi red for the otp write commands and the otp finalise command. it is also necessary to overdr ive the ldo12vout pin from an external supply. see section 6 for details of the required supply voltages. 14.4.1 entering / exiting the program state the ice and otp commands are only supported when the WM8310 is in the program state. the WM8310 can only enter the program state as a trans ition from the off state. this is commanded by setting the otp_prog register bit. important note - when the program state is selected, the WM8310 will read all pages of the otp memory into the corresponding pages of the dcrw. this is required in order to confirm if the otp contents have already been finalised (see section 14.4.5). the previous contents of the dcrw registers will be lost when the program state is entered. the transition into the program state can be conf irmed by reading the main_state register field as defined in section 11.2. when the main_state register reads back a value of 01011, then the WM8310 is in the program state. in the program state, the ice and otp commands are initiated by further writes to the otp control register (r16394), as described in the following sections. to exit the program state and resume normal operations, a device reset must be scheduled. 14.4.2 otp / ice read command the read command loads either one or all data pages from the ice or otp into the corresponding page(s) of the dcrw. the read commands are selected by writing 1 to the otp_read bit. to read the otp, the otp_mem bit should be set to 1. to read the ice, the otp_mem bit should be set to 0. the read margin level is selected by setting the otp_ read_lvl. note that this register relates to the otp only; it has no effect on ice read commands. the recommended setting for the otp read command is ?normal? level. the otp_read_lvl field should be set to 00b. to read a single memory page, the applicable page is selected by setting the otp_page field. to read all memory pages, the otp_bulk bit should be set to 1. note that the otp_page field is defined different ly for ice pages and for otp pages, as detailed in section 14.4.6. all other bits in the otp control register shoul d be set to 0 when a read command is issued. (note that otp_prog should be set to 0 when a read command is issued.) for typical applications, the bulk read commands are recommended. the otp control register contents for the otp / ice bulk read commands are detailed in table 23. read command otp control register value ice read all 0120h otp read all 2120h table 23 otp / ice read command
pre-production WM8310 w pp, may 2012, rev 3.1 59 14.4.3 otp write command the write command programs one or more data pages of the otp with data from the corresponding page(s) of the dcrw. the write commands are se lected by writing 1 to the otp_write bit. the otp memory is selected by setting the otp_mem bit to 1. (note that the WM8310 does not support programming the external ice memory.) to write a single memory page, the applicable page is selected by setting the otp_page field. to write all memory pages, the otp_bulk bit should be set to 1. note that page 0 and page 1 will be programmed during manufacture, and cannot be re-written. otp write is then only possible to page 2 and page 3. se lecting the otp_bulk bit will select otp write to page 2 and page 3 only. note that selecting the otp_bulk option will cause an otp error to be indicated (see section 14.5). this is because the bulk write to page 0 and page 1 is not permitted after the factory configuration of the WM8310. it is still possible to verify the otp bulk write, but the otp_err_eint flag must be cleared before doing so. the recommended procedure is to write page 2 and page 3 using single page otp write commands. all other bits in the otp control register shoul d be set to 0 when a write command is issued. (note that otp_prog should be set to 0 when a write command is issued.) the programming supply voltage progvdd is requir ed for the otp write command. it is also necessary to overdrive the ldo12vout pin from an ex ternal supply. see section 6 for details of the required supply voltages. for typical applications, it is recommended to write page 2 and page 3 in two separate commands. the otp control register contents for these otp write commands are detailed in table 24. write command otp control register value otp write page 2 2202h otp write page 3 2203h table 24 otp write command 14.4.4 otp verify command the verify command compares one or all data pages of the otp with data in the corresponding page(s) of the dcrw. the verify commands are selected by writing 1 to the otp_verify bit. the otp memory is selected by setting the otp_mem bit to 1. (note that the WM8310 does not support verifying the external ice memory.) the read margin level is selected by setting the otp_read_lvl. the recommended setting for the otp verify command is margin 1. the otp_read_lvl field should be set to 10b. to verify a single memory page, the applicable page is selected by setting the otp_page field. to verify all memory pages, the otp_bulk bit should be set to 1. all other bits in the otp control register should be set to 0 when a verify command is issued. (note that otp_prog should be set to 0 when a verify command is issued.) if the otp verify operation is unsuccessful (i e. the WM8310 detects a difference between the selected pages of the otp and dcrw memories), t hen this is indicated by the otp_err_eint interrupt flag, as described in section 14.5. note that, when verifying the otp after it has been finalised, the cust_otp_final bit needs to be set in the dcrw using a register write to r 30736 prior to the otp_verify operation. this is because the otp_final command does not set the cus t_otp_final bit in the dcrw; it only sets it in the otp memory. if the cust_otp_final bit is not set in dcrw, then the otp_verify command will result in an otp error indication. the otp control register contents for all ot p verify commands are detailed in table 25.
WM8310 pre-production w pp, may 2012, rev 3.1 60 verify command otp control register value otp verify page 0 2480h otp verify page 1 2481h otp verify page 2 2482h otp verify page 3 2483h otp verify all 24a0h table 25 otp verify command (margin 1) 14.4.5 otp finalise command the finalise command sets the otp finalise bit for the user-programmable pages of the otp memory. the finalise commands are selected by writing 1 to the otp_final bit. note that page 0 and page 1 will be programmed and finalised during manufacture; these memory pages cannot be re-written by users. following the user finalise command, page 2 and page 3 of the otp memory will be prevented from any further otp write commands. each page of the otp memory can be programmed only once; the otp finalise command ensures that any subsequent write commands will have no effect and that the otp contents are maintained securely. the otp memory is selected by setting the otp_mem bit to 1. (note that the WM8310 does not support this function on the external ice memory.) the customer finalise bit (cust_otp_final) is in page 2. this page is selected by setting otp_page = 10. note that the page 2 finalise bit locks the contents of page 2 and page 3. all other bits in the otp control register s hould be set to 0 when a finalise command is issued. (note that otp_prog should be set to 0 when a finalise command is issued.) the programming supply voltage progvdd is requir ed for the otp finalise command. it is also necessary to overdrive the ldo12vout pin from an ex ternal supply. see section 6 for details of the required supply voltages. note that the otp_final command does not set the cust_otp_final bit in the dcrw; it only sets it in the otp memory. care is required when verifying a finalised otp page, to avoid an otp error indication, as described in section 14.4.4. the otp control register contents for the otp fina lise command is detailed in table 26. this is the only recommended otp finalise command; no variant s of the finalise command should be used. finalise command otp control register value otp finalise page 2 (note that this command finalises the contents of otp page 2 and page 3.) 2802h table 26 otp finalise command
pre-production WM8310 w pp, may 2012, rev 3.1 61 14.4.6 otp control register the otp control register (r16394) is defined in t able 27. note that some of the otp programming registers are locked by the WM8310 user key. t hese registers can only be changed by writing the appropriate code to the security register, as described in section 12.4. address bit label default description r16394 (400ah) otp control 15 otp_prog 0 selects the program device state. 0 = no action 1 = select program mode note that, after program mode has been selected, the chip will remain in program mode until a device reset. protected by user key 13 otp_mem 1 selects ice or otp memory for program commands. 0 = ice 1 = otp protected by user key 11 otp_final 0 selects the finalise command, preventing further otp programming. 0 = no action 1 = finalise command protected by user key 10 otp_verify 0 selects the verify command for the selected otp memory page(s). 0 = no action 1 = verify command protected by user key 9 otp_write 0 selects write command for the selected otp memory page(s). 0 = no action 1 = write command protected by user key 8 otp_read 0 selects read command for the selected memory page(s). 0 = no action 1 = read command protected by user key 7:6 otp_read_l vl [1:0] 00 selects the margin level for read or verify otp commands. 00 = normal 01 = reserved 10 = margin 1 11 = margin 2 protected by user key 5 otp_bulk 0 selects the number of memory pages for ice / otp commands. 0 = single page 1 = all pages 1:0 otp_page [1:0] 00 selects the single memory page for ice / otp commands (when otp_bulk=0). if otp is selected (otp_mem = 1): 00 = page 0 01 = page 1 10 = page 2 11 = page 3
WM8310 pre-production w pp, may 2012, rev 3.1 62 address bit label default description if ice is selected (otp_mem = 0): 00 = page 2 01 = page 3 10 = page 4 11 = reserved table 27 otp memory control 14.5 otp / ice interrupts the otp and ice memories are associated with two interrupt event flags. the otp_cmd_end_eint interrupt is set each ti me an otp / ice command has completed or if otp auto-program has completed. (see section 14.4 for a definition of the otp and ice commands. see section 14.6.3 for details of the otp auto-program function.) the otp_err_eint interrupt is set when an otp / ice error has occurred. the errors detected include ice read failure, otp verify failure and attempted otp write to a page that has been finalised. each of these secondary interrupts triggers a primary otp memory interrupt, otp_int (see section 23). this can be masked by setting t he mask bit(s) as described in table 70. note that otp_cmd_end_eint is triggered dur ing the normal start-up and shutdown operations, when the WM8310 accesses the otp and/or ice memories. for typical applications, it is recommended that the otp_cmd_end_eint interrupt should be masked at all times except when performing user-initiated otp/dbe commands. address bit label description r16402 (4012h) interrupt status 2 5 otp_cmd_end_eint otp / ice command end interrupt (rising edge triggered) note: cleared when a ?1? is written. 4 otp_err_eint otp / ice command fail interrupt (rising edge triggered) note: cleared when a ?1? is written. r16410 (401ah) interrupt status 2 mask 5 im_otp_cmd_end_eint interrupt mask. 0 = do not mask interrupt. 1 = mask interrupt. default value is 1 (masked) 4 im_otp_err_eint interrupt mask. 0 = do not mask interrupt. 1 = mask interrupt. default value is 1 (masked) table 28 otp memory interrupts 14.6 dcrw memory contents the dcrw is the ice/otp register window, as de scribed in section 14.2. under normal operating conditions, this memory area is initialised with data from the integrated otp or an external ice memory. the dcrw memory addresses range from r30720 (7800h) to r30759 (7827h). the complete register map definition is described in section 28. the register fields in the dcrw allow the start- up configuration of the dc-dc converters, the ldo regulators, gpio pins 1-6 and status led output s to be programmed. the dcrw also provides control of the battery charger, clocking, usb current limit and the start-up (sysok) voltage threshold.
pre-production WM8310 w pp, may 2012, rev 3.1 63 most of the dcrw contents are duplicates of control registers that exist in the main register area below the dcrw addresses. in theses cases, reading or writing to either address will have the same effect. some register fields are defined only in the dcrw area; a detailed description of these fields is provided in the following sub-sections. 14.6.1 dcrw page 0 page 0 of the dcrw occupies register addresse s r30720 (7800h) to r30727 (7807h). this contains factory-preset data which is loaded from ot p when an ?on? state transition is scheduled. page 0 of the dcrw contains a 128-bit unique id. note that these fields are read-only in the otp and cannot be changed. 14.6.2 dcrw page 1 page 1 of the dcrw occupies register addresse s r30728 (7808h) to r30735 (780fh). this contains factory-preset data which is loaded from ot p when an ?on? state transition is scheduled. page 1 of the dcrw contains trim parameters that ensure the accuracy of the voltage references and the power management rc oscillator. note that these fields are read-only in the otp and cannot be changed. 14.6.3 dcrw page 2 page 2 of the dcrw occupies register addresse s r30736 (7810h) to r30743 (7817h). this contains user-programmable data. this page of data is normally loaded from otp when ?on? state transition is scheduled (except in development mode or if reconfig_at_on = 0) . this page of data can also be loaded from otp using the otp_read command; it can be written to the otp using the otp_write command. this page of data is loaded from the first page of ice memory (00h to 0fh) when ?on? state transition is scheduled in development mode (if reconfig _at_on = 1). this page of data can also be loaded from ice using the ice read command. note that ice address 00h corresponds to bits 15:8 at the start address of dcrw page 2; ice address 01h corresponds to bits 7:0 at the same dcrw address. if the WM8310 configuration data is loaded from exter nal ice in response to an ?on? state transition request, and the otp_auto_prog register bit is set, then the WM8310 will program the otp with the contents page 2 and page 3 of the dcrw data, after the ice data has been loaded and confirmed as valid. the WM8310 will also perform a margin 1 verify as part of the auto-program function. the programming supply voltage progvdd is requi red for the otp_auto_prog command. it is also necessary to overdrive the ldo12vout pin from an external supply. see section 6 for details of the required supply voltages. using the auto-program function described above, the otp will be finalised if the otp_cust_final bit is set in the ice data. completion of the auto- program is indicated using the otp interrupts, as described in section 14.5. the auto-program completi on is also indicated on the status led outputs, as described in section 22. the otp_cust_id field is used to hold a customer identifier for the otp data contents. whenever an ?on? state transition is requested, then the otp_ cust_id field is checked to confirm valid otp data. if the otp_cust_id field is set to zero, then the WM8310 remains in the off power state. a non-zero otp_cust_id field is used to confirm valid otp contents. the otp_cust_final bit is used to control w hether the user-programmable otp data (page 2 and page 3) is finalised. if otp_cust_final is set in the otp and also set in the dcrw, then the WM8310 prevents any further writes to the otp. if the dcrw has been loaded from the otp, then the otp_cust_final bit indicates whether any fu rther write operations are possible. if the dcrw
WM8310 pre-production w pp, may 2012, rev 3.1 64 has been loaded from the ice, and the otp auto-pr ogramming option is selected (see above), then the value of the otp_cust_final bit will be copied from the ice memory to the otp memory. the above registers are defined in table 29. address bit label default description r30736 (7810h) customer otp id 15 otp_auto_ prog 0 if this bit is set when bootstrap data is loaded from ice (in development mode), then the ice contents will be programmed in the otp. 14:1 otp_cust_ id [13:0] 0000h this field is checked when an ?on? transition is requested. a non-zero value is used to confirm valid data. 0 otp_cust_ final 0 if otp_cust_final is set in the otp and also set in the dcrw, then no further writes are possible to the otp. table 29 otp registers - dcrw page 2 the remaining contents of dcrw page 2 include the r egisters listed in table 30, which are defined in other sections of this datasheet. register function reference dc1_on_slot [2:0] dc-dc converter 1 see section 15.12.2 dc1_freq [1:0] see section 15.12.2 dc1_phase see section 15.12.2 dc1_on_vsel [6:2] see section 15.12.2 dc1_cap [1:0] see section 15.12.2 dc2_on_slot [2:0] dc-dc converter 2 see section 15.12.2 dc2_freq [1:0] see section 15.12.2 dc2_phase see section 15.12.2 dc2_on_vsel [6:2] see section 15.12.2 dc2_cap [1:0] see section 15.12.2 dc3_on_slot [2:0] dc-dc converter 3 see section 15.12.2 dc3_phase see section 15.12.2 dc3_on_vsel [6:2] see section 15.12.2 dc3_cap [1:0] see section 15.12.2 ldo1_on_slot [2:0] ldo regulator 1 see section 15.12.4 ldo1_on_vsel [4:0] see section 15.12.4 ldo2_on_slot [2:0] ldo regulator 2 see section 15.12.4 ldo2_on_vsel [4:0] see section 15.12.4 ldo3_on_slot [2:0] ldo regulator 3 see section 15.12.4 ldo3_on_vsel [4:0] see section 15.12.4 ldo4_on_slot [2:0] ldo regulator 4 see section 15.12.4 ldo4_on_vsel [4:0] see section 15.12.4 ldo5_on_slot [2:0] ldo regulator 5 see section 15.12.4 ldo5_on_vsel [4:0] see section 15.12.4 ldo6_on_slot [2:0] ldo regulator 6 see section 15.12.4 ldo6_on_vsel [4:0] see section 15.12.4 ldo7_on_slot [2:0] ldo regulator 7 see section 15.12.4 ldo7_on_vsel [4:0] see section 15.12.4 ldo8_on_slot [2:0] ldo regulator 8 see section 15.12.4 ldo8_on_vsel [4:0] see section 15.12.4 table 30 dcrw page 2
pre-production WM8310 w pp, may 2012, rev 3.1 65 14.6.4 dcrw page 3 page 3 of the dcrw occupies register addresse s r30744 (7818h) to r30751 (781fh). this contains user-programmable data. this page of data is normally loaded from otp when ?on? state transition is scheduled (except in development mode or if reconfig_at_on = 0) . this page of data can also be loaded from otp using the otp_read command; it can be written to the otp using the otp_write command. this page of data is loaded from the second page of ice memory (10h to 1fh) when ?on? state transition is scheduled in development mode (if re config_at_on = 1). this page of data can also be loaded from ice using the ice read command. no te that ice address 10h corresponds to bits 15:8 at the start address of dcrw page 3; ice address 11h corresponds to bits 7:0 at the same dcrw address. the contents of dcrw page 3 include the registers listed in table 31. register function reference ldo9_on_slot [2:0] ldo regulator 9 see section 15.12.4 ldo9_on_vsel [4:0] see section 15.12.4 ldo10_on_slot [2:0] ldo regulator 10 see section 15.12.4 ldo10_on_vsel [4:0] see section 15.12.4 ldo11_on_slot [2:0] ldo regulator 11 see section 15.12.4 ldo11_on_vsel [3:0] see section 15.12.4 epe1_on_slot [2:0] external power converter enable see section 15.12.5 epe2_on_slot [2:0] see section 15.12.5 gp1_dir gpio1 see section 21.3 gp1_pull [1:0] see section 21.3 gp1_int_mode see section 21.3 gp1_pwr_dom see section 21.3 gp1_pol see section 21.3 gp1_od see section 21.3 gp1_ena see section 21.3 gp1_fn [3:0] see section 21.3 gp2_dir gpio2 see section 21.3 gp2_pull [1:0] see section 21.3 gp2_int_mode see section 21.3 gp2_pwr_dom see section 21.3 gp2_pol see section 21.3 gp2_od see section 21.3 gp2_ena see section 21.3 gp2_fn [3:0] see section 21.3 gp3_dir gpio3 see section 21.3 gp3_pull [1:0] see section 21.3 gp3_int_mode see section 21.3 gp3_pwr_dom see section 21.3 gp3_pol see section 21.3 gp3_od see section 21.3 gp3_ena see section 21.3 gp3_fn [3:0] see section 21.3 gp4_dir gpio4 see section 21.3 gp4_pull [1:0] see section 21.3 gp4_int_mode see section 21.3 gp4_pwr_dom see section 21.3 gp4_pol see section 21.3 gp4_od see section 21.3 gp4_ena see section 21.3 gp4_fn [3:0] see section 21.3
WM8310 pre-production w pp, may 2012, rev 3.1 66 register function reference gp5_dir gpio5 see section 21.3 gp5_pull [1:0] see section 21.3 gp5_int_mode see section 21.3 gp5_pwr_dom see section 21.3 gp5_pol see section 21.3 gp5_od see section 21.3 gp5_ena see section 21.3 gp5_fn [3:0] see section 21.3 gp6_dir gpio6 see section 21.3 gp6_pull [1:0] see section 21.3 gp6_int_mode see section 21.3 gp6_pwr_dom see section 21.3 gp6_pol see section 21.3 gp6_od see section 21.3 gp6_ena see section 21.3 gp6_fn [3:0] see section 21.3 clkout_slot [2:0] clocking see section 13.1 clkout_src see section 13.1 xtal_ena see section 13.1 xtal_inh see section 13.1 fll_auto_freq [2:0] see section 13.3 usb_ilim [2:0] usb configuration see section 17.4 usb100ma_startup [1:0] see section 17.4 chg_ena battery charger enable see section 17.7 wdog_ena watchdog timer see section 25 led1_src [1:0] system status led drivers see section 22.2 led2_src [1:0] see section 22.2 sysok_thr [2:0] supply voltage monitoring see section 24.4 table 31 dcrw page 3 14.6.5 dcrw page 4 page 4 of the dcrw occupies register addresses r30752 (7820h) to r30759 (7827h). this page of data is loaded from the third page of ice memory (20h to 2fh) when ?on? state transition is scheduled in development mode. this page of data can also be loaded from ice using the ice read command. note that ice address 20h corresponds to bits 15:8 at the start address of dcrw page 4; ice address 21h corresponds to bits 7:0 at the same dcrw address. the ice_valid_data register is used to hold a va lidation field for the ice data contents. if the WM8310 configuration data is loaded from the external ice in response to an ?on? state transition request in development mode, then the ice_valid_dat a field is checked to confirm valid ice data. the ice data is deemed valid if the ice_valid_data field contains the value a596h. if the ice is not connected or contains invalid data, then the WM8310 remains in the off power state until a device reset. the ice_valid_data register is defined in table 32. address bit label default description r30759 (7827h) ice check data 15:0 ice_valid_ data [15:0] 0000h this field is checked in development mode when an ?on? transition is requested. a value of a596h is required to confirm valid data. table 32 ice registers - dcrw page 4
pre-production WM8310 w pp, may 2012, rev 3.1 67 15 power management 15.1 general description the WM8310 provides 4 dc-dc converters and 11 ldo regulators. the dc-dc converters comprise 3 step-down (buck) converters and 1 step- up (boost) converter. the regulators comprise general purpose ldos (ldo1 - ldo6) and low-noi se analogue ldos (ldo7 - ldo10). the analogue ldos offer superior psrr, noise and load-transi ent performance. ldo11 is a low power ldo intended for powering ?always on? circuits connect ed to the WM8310; this ldo can be configured to remain enabled in the off state. these power management components are desi gned to support application processors and associated peripherals. dc-dc1 and dc-dc2 are int ended to provide power to the processor voltage domains; dc-dc3 is suitable for power ing memory circuits or for use as a pre-regulator for the ldos. the output voltage of each of the buck converte rs and regulators is programmable in software through control registers. the WM8310 can execute programmable sequences of enabling and disabling the dc-dc buck converters and ldo regulators as part of the transitions between the on, off and sleep power states. the WM8310 power management circuits can also interface with configurable hardware control functions supported via gpio pins. these include gpio inputs for selecting alternate voltages or operating modes, and gpio outputs for cont rolling external power management circuits. the configuration of the power m anagement circuits, together with so me of the gpio pins and other functions, may be stored in the integrated ot p memory. this avoids any dependence on a host processor to configure the WM8310 at start-up. see section 14 for details of the otp memory. 15.2 dc-dc converter and ldo regulator control the integrated dc-dc converters and ldo regul ators can each be enabled in the on or sleep power states by setting the dc m _ena or ldo n _ena bits as defined in section 15.12.1. note that setting the dc m _ena or ldo n _ena bits in the off state will not enable the dc-dc converters or ldo regulators. these bits should not be written to when the WM8310 is in the off state; writing to these bits in the off stat e may cause a malfunction. in many applications, there will be no need to write to the dc m _ena or ldo n _ena bits, as these bits are controlled by the WM8310 when a power state tr ansition is scheduled. dynam ic, run-time control of the dc-dc converters or ldo regulators is also po ssible by writing to these registers. note that the dc-dc4 boost converter cannot be configured as part of the power state transitions; this converter must always be enabled by writing to the dc4_ena bit. the dc-dc converters and ldo regulators can be a ssigned to a hardware enable (gpio) input for external enable/disable control. in this case, t he converter or regulator is not affected by the associated dc m _ena or ldo n _ena bits. see section 15.3 for further details. the WM8310 can also control other circuits, including external dc-dc converters or ldo regulators using the external power enable (epe) outputs. the external power enable outputs are alternate functions supported via gpio - s ee section 21. the external power enable outputs can be controlled in the same way as the internal dc-dc converters and ldo regulators. the associated control bits are epe1_ena and epe2_ena, as defined in section 15.12.1. ldo regulator 11 is a low power ldo regulator, whic h is configured differently to the other ldos. it is a low-power ldo intended for ?always-on? f unctions external to the WM8310 and can be enabled when the WM8310 is in the off power state. when ldo11_frcena is set, then ldo11 is enabled at all times in the off, on and sleep states. note that ldo11 is always disabled in the bac kup and no power states. see section 15.12.4 for the definition of ldo11_frcena. the current commanded state of each of the dc-dc converters, ldo regulators and epe outputs is indicated in the dc m _sts, ldo n _sts and epe n _sts register bits. if a fault condition causes any c onverter or regulator to be dis abled, then the associated _ena and _sts fields are reset to 0.
WM8310 pre-production w pp, may 2012, rev 3.1 68 15.3 timeslot control and hardware enable (gpio) control the dc-dc converters 1-3 and ldo regulators 1-11 may be programmed to switch on in a selected timeslot within the on sequence using the dc m _on_slot or ldo n_on_slot fields. these register fields are defined in section 15.12.2 and se ction 15.12.4. alternatively, these fields can be used to assign a converter / regulator to one of the hardware enable inputs. (the hardware enable inputs are alternate functions suppor ted via gpio - see section 21.) converters / regulators which are assigned to one of the hardware enable inputs are enabled or disabled according to the logic level of the respec tive gpio input in the on or sleep power states. the hardware enable inputs are effective from the end of the on sequence until the start of the off sequence. note that the gpio hardware enable f unction is not the same as the gpio hardware control function. any converters / regulators which are assigned to timeslots within the on sequence will be disabled in the reverse sequence when an off sequence is scheduled. any converters / regulators which are not assigned to timeslots, or are assigned to hardwa re enable inputs, will be disabled immediately at the start of the off sequence. each of the converters / regulators may also be programmed to be disabled in a selected timeslot within the sleep sequence using the dc m _slp_slot or ldo n_slp_slot fields. in the case of converters / regulators which are not disabled by the sleep sequenc e, these fields determine in which timeslot each converter or regul ator enters its sleep configuration. any converters / regulators which are disabled as part of t he sleep sequence will be enabled in the reverse sequence when a wake transition is scheduled. by default, the off sequence is the reverse of t he on sequence. similarl y, the wake sequence is the reverse of the sleep sequence. if a different behaviour is required, th is can be achieved by writing to the _on_slot or _slp_slot register s between transitions in order to re-define the sequences. any converters / regulators which are assigned to hardware enable inputs will remain under control of the hardware enable inputs in the sleep power state. in this case, the dc m _slp_slot or ldo n_slp_slot fields determine in which timeslot the converter / regulator enters its sleep configuration. the WM8310 will control the dc m _ena or ldo n _ena bit (see section 15.2) for any converter / regulator that is enabled or disabled during the power state transitions. in the case of a converter / regulator assigned to a hardware enable (gpio) input, the dc m _ena or ldo n _ena bit is not controlled and the converter / regulat or is not affected by this bit. the dc-dc converters include a soft-start feature that limits in-rush current at start-up. however, in order to further reduce supply in-rush current, it is recommended that the i ndividual converters are programmed to start up in different time slot s within the start-up sequence, as described in section 11.3. similarly, it is recommended that the individual ldo regulators are programmed to start up in different time slots within the start-up sequence, as described in section 11.3. note that the dc-dc4 boost converter cannot be c onfigured as part of the power state transitions; this converter must always be enabled by writing to the dc4_ena bit. the external power enable (epe) outputs, epe1 and epe2, may also be assigned to timeslots in the on / sleep sequences or assigned to ha rdware enable inputs using the epe n_on_slot and epen_slp_slot fields described in 15.12.5. note that a transition from the sleep state to the off state is not a controlled transition. if an ?off? event occurs whilst in the sleep state, then the WM8310 will select the off state, but all the enabled converters and regulators w ill be disabled immediately ; the time-controlled sequence is not implemented in this case. see section 11.3 for details of the WM8310 ?off? events.
pre-production WM8310 w pp, may 2012, rev 3.1 69 15.4 operating mode control 15.4.1 dc-dc synchronous buck converters the dc-dc (buck) converters dc-dc1, dc-dc2 and dc-dc3 can be configured to operate in four different operating modes. the operating modes ar e summarised in table 33. for more detailed information on the dc-dc (buck) converte r operating modes, see section 15.15.2. dc-dc converter operating mode description forced continuous conduction mode (fccm) high performance mode for all static and transient load conditions. auto mode: continuous / discontinuous conduction with pulse-skipping mode (ccm/dcm with ps) high efficiency mode for all static and transient load conditions. performance may be less than fccm mode for heavy load transients. hysteretic mode high efficiency mode for light static and light transient loads only. maximum load current is restricted; output voltage ripple is increased. ldo mode power saving mode for light loads only. high efficiency for ultra light loads. low current soft-start control. table 33 dc-dc synchronous buck converters operating modes the operating mode of the dc-dc converters in the on power state is selected using the dc m _on_mode register fields. the operating mode of the dc-dc converters in the sleep power state is selected using the dc m _slp_mode register fields. when changing the operating mode of the dc-dc conver ters in preparation for an increased load, a set-up time of 100 ? s should be allowed for the operating mode to be established before applying the new load. note that the operating mode of the dc-dc conver ters may also be controlled by the hardware control inputs. the hardware control inputs ar e alternate functions supported via gpio. see section 15.9 for details of hardware control. note that, for minimum dc-dc3 quiescent current in ldo mode, the converter must first be enabled in fccm, ccm/dcm with ps or hysteretic mode, before ldo mode is selected. 15.4.2 dc-dc boost converters the dc-dc4 boost converter is enabled by setting t he dc4_ena bit as described in section 15.2. note that this converter cannot be enabled automatica lly under timeslot control in the on transition. however, the converter can either be disabled or unchanged in the sleep transition, as determined by dc4_slpena. the boost converter is intended to be used as a power supply for either of the current sinks, isink1 or isink2 (see section 16). the boost converter must be configured for the applicable current sink using the dc4_fbsrc bit. when the dc-dc4 boost converter is enabled, its output voltage is regulated in such a way that the selected isink voltage (at isink1 or isink2) is 0.5v. output voltages of up to 30v can be generated in order to support the current that has been sele cted for the isink. the required voltage range must be set using the dc4_range field in order to ensure stable operation. if the boost converter is used to provide a supply for both isinks simultaneously, then the dc4_range and dc4_fbsrc bits should be set accordi ng to whichever of the isinks requires the higher supply voltage. 15.4.3 ldo regulators the ldo regulators ldo1 - ldo10 can be configur ed to operate in normal operating mode or in low power mode.
WM8310 pre-production w pp, may 2012, rev 3.1 70 the operating mode of the ldo regulators in the on power state is selected using the ldo n _on_mode register fields. the operating m ode of the ldo regulators in the sleep power state is selected using the ldo n _slp_mode register fields. for the standard ldos, ldo1 - ldo6, two different low power modes are provided, offering limited load current capability and reduced quiescent curren t. when low power mode is selected in the on or sleep power states, then the ldo n _lp_mode register bits determine which low power mode is selected. note that the operating mode and output voltage of the ldo regulators may also be controlled by the hardware control inputs. the hardware control inputs are alternate func tions supported via gpio. see section 15.9 for details of hardware control. 15.5 output voltage control 15.5.1 dc-dc synchronous buck converters the output voltage of the dc-dc converters 1-3 in the on power state is selected using the dc m _on_vsel register fields. the output voltage of these converters in the sleep power state is selected using the dc m _slp_vsel register fields. dc-dc converters 1 and 2 support two different swit ching frequencies, as described in section 15.6. note that the supported output voltage range for these converters is restricted in the 4mhz mode; for output voltages greater than 1.4v, the 2mhz mode must be used. the dc-dc converters are dynamically progra mmable - the output voltage may be adjusted in software at any time. these converters are step- down converters; their output voltage can therefore be lower than the input voltage, but cannot be higher. note that the output voltage of dc-dc converters 1 and 2 may also be controlled using the dynamic voltage scaling features described in section 15. 6. software control (using register writes) and hardware control (using the hardware dvs cont rol inputs supported via gpio) is supported. note that the output voltage of the dc-dc converters may also be controlled by the hardware control inputs. the hardware control inputs ar e alternate functions supported via gpio. see section 15.9 for details of hardware control. when changing the output voltage of dc-dc conv erters 1 and 2, the gpio output ?dc-dc m dvs done? can be used to confirm the dvs control has completed; see section 15.6 for details. 15.5.2 dc-dc boost converters the output voltage of the dc-dc4 boost converter is set as described in section 15.4.3. the voltage is not commanded directly, but is regulated automatically by the WM8310 in order to support the current that has been commanded for the selected current sink (isink). 15.5.3 ldo regulators 1-10 the output voltage of the ldo regulators 1-10 in the on power state is selected using the ldo n _on_vsel register fields. the output voltage of the ldo regulators in the sleep power state is selected using the ldo n _slp_vsel register fields. the ldo regulators are dynamically programmable - the output voltage may be adjusted in software at any time. note that the output voltage of the ldo regulators may also be controlled by the hardware control inputs. the hardware control inputs are alternate functions supported via gp io. see section 15.9 for details of hardware control. 15.5.4 ldo regulator 11 the output voltage of ldo11 can be set in two ways - it can be commanded directly, or it can be commanded to follow the dc-dc converter 1 output voltage.
pre-production WM8310 w pp, may 2012, rev 3.1 71 when ldo11_vsel_src = 0, then the output voltage of ldo11 is set by ldo11_on_vsel (in the on state) or by ldo11_slp_vsel (in the sleep state) in the same way as the other ldos. when ldo11_vsel_src = 1, the output voltage of ldo11 follows the output voltage of dc-dc converter 1. this enables both dom ains to be changed at the same time, eg. the processor core and processor ?alive? domains. in this case, t he ldo11 output voltage follows dc1_on_vsel or dc1_slp_vsel in the on state or sleep state respectively. note that, when ldo11_vsel_src = 1, the ldo 11 regulator adopts the nearest achievable output voltage, which may not be identical to the dc-dc1 voltage, due to the more limited range and resolution of ldo11 - the output voltage of ldo11 is in the range 0.8v to 1.55v in 50mv steps; the output voltage of dc-dc1 is in the range 0.6v to 1.8v in 12.5mv steps. if dc-dc1 is disabled, then the ldo11 voltage tracking feature is not supported, and the ldo11 output voltage will be 0.8v. 15.6 dc-dc synchronous buck converter control soft-start control is provided for each of t he dc-dc synchronous buck converters, using the dc m _soft_start register fields. w hen a dc-dc converter is switched on, the soft-start circuit will apply current limiting in order to control the in-rush current. for dc-dc1 and dc-dc2, the current limit is increased through up to 8 stages to the full load condition. the dcm_soft_start registers select the duration of these stages. (note that, under light loads, the full start-up may be achieved in fewer than 8 stages.) a similar function is prov ided for dc-dc3, but only 3 intermediate stages are implemented for this converter. when dc-dc3 is operating in hysteretic mode, t he maximum dc output current can be set using the dc3_stnby_lim register. see section 15.4.1 for details of the dc-dc3 operating modes. to ensure stable operation, the register fields dc m _cap must be set for each of the dc-dc converters according to the output capacitance. (not e that these fields are set via otp/ice settings only; they cannot be changed by writing to the contro l register.) the choice of output capacitor is described in section 30.3. when a dc-dc converter is disabled, the output pin can be configured to be floating or to be actively discharged. this is selected using dc m _flt. dc-dc converters 1 and 2 also support selectable sw itching frequency. this can either be 2mhz or 4mhz, according to the dc m _freq register field. (note that these fields are set via otp/ice settings only; they cannot be changed by writing to the control register.) the switching frequency of dc-dc3 is fixed at 2mhz. note that the supported output voltage range for dc-dc converters 1 and 2 is restricted in the 4mhz mode; for output voltages greater than 1.4v, the 2mhz mode must be used. the switching phase of each dc-dc c onverter can be set using the dc m _phase bits. where two converters are operating at the same switching frequency, the supply current ripple can be minimised by selecting a different switching phase for each converter. the dynamic voltage scaling (dvs) feature on dc-dc1 and dc-dc2 enables hardware or software selection of an alternate output voltage, dc m _dvs_vsel. this may be useful if a short-term variation in output voltage is required. the dvs voltage (set by dc m _dvs_vsel) may be selected by setting dc m _dvs_src = 01. alternatively, the dvs voltage may be selected under control of one of the hardware dvs control inputs supported via the gpio pins. see section 21 for details of configur ing the gpio pins as hardware dvs control inputs. whenever the dvs voltage is selected by any met hod, the dvs selection takes precedence over the on, sleep or hardware control (hwc) configuration. see section 15.9 for details of hardware control options. the output voltage ramp rate is selectable for dc-dc converters 1 and 2. the dc m _rate field selects the rate of change of output voltage, whether this is in response to an operating mode transition, or any hardware or software command. note that the dc m _rate field is accurate in forced continuous conduction mode (fccm); in other modes, the actual slew rate may be longer in the case of a decreasing output voltage sele ction, especially under light load conditions.
WM8310 pre-production w pp, may 2012, rev 3.1 72 the WM8310 can indicate the status of the dynamic voltage scaling via a gpio pin configured as a ?dc-dc1 dvs done? or ?dc-dc2 dvs done? out put (see section 21). when a gpio pin is configured to indicate the dvs status, this signal is temporarily de-asserted during a dvs transition on the associated dc-dc converter, and is subsequent ly asserted to indicate the transition has completed. note that the gpio dvs outputs indicate the progre ss of all output voltage slews; they are not limited to transitions associated with dc m _dvs_src; the gpio dvs output also indicates the status of a slew caused by a write to the dc m _on_vsel register, or a slew to the dc m _slp_vsel voltage. note also that the gpio dvs outputs are indicators of the dvs control mechanism only; they do not confirm the output voltage accuracy. the output volt age can be checked using t he voltage status bits if required (see section 15.2). 15.7 dc-dc boost converter control the dc-dc4 boost converter is designed as a power source for the current sinks described in section 16. the associated control registers for dc-dc4 are described in section 15.4.2. the boost converter uses one or other of the curr ent sinks to provide voltage feedback in order to control the converter output voltage. the select ed current sink is determined by the dc4_fbsrc register bit. if the boost converter is used to provide a supply for both isinks simultaneously, then the dc4_range and dc4_fbsrc bits should be set acco rding to whichever of the isinks requires the higher supply voltage. it is important to follow the recommended control s equences for switching on/off the boost converter and current sinks. these sequences are described in section 16. the maximum current that can be supported by the b oost converter varies with the output voltage, as noted in the electrical charac teristics (see section 7.2). the current sinks are suited to controlling led backli ght circuits. at low output voltages (eg. 5v), the dc-dc4 boost converter is capable of supporting currents which exceed the maximum current rating of the current sinks. please contact wolfson app lications support if furt her guidance is required on configuring dc-dc4 for higher current t han is supported by the current sinks. 15.8 ldo regulator control the ldo regulators 1-10 can be configured to act as current limited switches by setting the ldo n _swi field. when this bit is selected, ther e is no voltage regulation and the operating mode and output voltage controls of the corresponding ldo are ignored. in switch mode, the switch is enabled (closed) and disabled (opened) by enabling or disabling the ldo. note that switch mode cannot be selected via the otp memory settings, and must be configured after the WM8310 has entered the on state. when the ldo regulator is disabled (and switch mode is not selected), the output pin can be configured to be floating or to be actively discharged. this is selected using ldo n _flt. 15.9 hardware control (gpio) the dc-dc converters, ldo regulators and epe outputs may be controlled by the hardware control inputs supported via the gpio pins. the dc m _hwc_src, ldo n _hwc_src or epe n _hwc_src fields determine which of these hardware control inputs is effective. see section 21 for details of configuring the gpio pins as hardware control inputs. note that the gpio hardware control function is not the sa me as the gpio hardware enable function. hardware control is only possible when the applicable dc m _ena, ldo n _ena or epe n _ena control bit is set (see section 15.2), or if a hardware enable has been assigned to the relevant function and is asserted. the action taken in response to the selected hard ware control inputs is configurable for each dc-dc converter, ldo regulator or epe output. t he available options are described below.
pre-production WM8310 w pp, may 2012, rev 3.1 73 when a hardware control input is assigned to a dc-dc buck converter (dc-dc1, dc-dc2 or dc- dc3), and is asserted, the operating mode and output voltage of the relevant dc-dc converter is determined by the dc m _hwc_vsel and dc m _hwc_mode fields; this takes precedence over the normal on or sleep settings. note that the hardware control input can be used to disable a dc-dc buck converter if required, by setting dc m _hwc_mode = 01. when a hardware control input is assigned to t he dc-dc4 boost converter, and is asserted, the converter is controlled as determined by the dc4_h wc_mode field; this takes precedence over the normal on or sleep settings. the available options ar e to disable the converter, or to remain under control of dc4_ena. when a hardware control input is assigned to ld o regulators 1-10, and is asserted, the operating mode and output voltage of the relevant ldo regulators is determined by the ldo n _hwc_vsel and ldo n _hwc_mode fields; this takes precedence over the normal on or sleep settings. note that, for the standard ldos (ldo1 - ldo6), when low power mode is selected (ldo n _hwc_mode = 00 or 10), then the low power mode type is determined by the ldo n _lp_mode register bits. when a hardware control input is assigned to t he external power enable (epe) outputs, and is asserted, the relevant epe outputs are controlled as determined by the epe n _hwc_ena field; this takes precedence over the normal on or sleep settings . the available options are to de-assert the epe, or for the epe to remain under control of epe n _ena. 15.10 fault protection each of the dc-dc buck converters (1 to 3) is monitored for voltage accuracy and fault conditions. an undervoltage condition is set if the output voltage falls below the required level by more than the applicable undervoltage margin, as specified in section 7.1. the dc-dc4 boost converter is monitored for vo ltage accuracy and fault conditions. the voltage at isink1 or isink2 is monitored as an indicator of an overcurrent condition. each ldo regulator (1 to 10) is monitored fo r voltage accuracy and fault conditions. an undervoltage condition is set if the output voltage falls below the required level by more than the undervoltage margin, as specified in section 7.4. the dc m _err_act and ldo n _err_act fields configure the fault response to an undervoltage condition. an interrupt is always triggered under this condition (see secti on 15.13); additional action can also be selected independently for each converter / regulator. the options are to ignore the fault, shut down the converter, or to shut down the syst em. to prevent false alar ms during short current surges, faults are only signalled if the fault condition persists. if a fault condition is detected, and the selected res ponse is to shut down the converter or regulator, then the associated _ena and _sts fields are reset to 0, as described in section 15.2. if a fault condition is detected, and the selected res ponse is to shut down the system, then a device reset is triggered, as described in section 24.1, forcing a transition to the off state. the WM8310 will automatically return to the on state after performing the device reset. note that, if the fault condition persists, then a maximum of 6 device resets will be attempted to initiate the start-up sequence. if the sequence fails more than 6 times, the WM8310 will remain in the off state until the next valid on state transition event occurs. note that the dc-dc4 boost converter will not be automatically enabled following a device reset; this must be re-enabled using the dc4_ena bit if required. note that dc-dc1 and dc-dc2 overvoltage and high current conditions can be detected and reported as described in section 15.11. the dc m _err_act fields have no relation to these conditions.
WM8310 pre-production w pp, may 2012, rev 3.1 74 the dc-dc3 buck converter has a selectable ov ervoltage protection feature, controlled by dc3_ovp. this affects the converter response when dc3 is enabled or when its output voltage is increased. when the overvoltage protection is enabled, there is less overshoot in the output voltage, but some oscillation may occur as the voltage se ttles. this function s hould only be enabled if steep load transients are present on the output of dc-dc3 and if voltage overshoot is critical. 15.11 monitoring and fault reporting each of the dc-dc converters (1 to 4) and ldos (1 to 10) is monitored for voltage accuracy and fault conditions. an undervoltage condition is detected if the voltage falls below the required level by more than a pre-determined tolerance. if an undervoltage condi tion occurs, then this is indicated using the corresponding status bit(s) defined in section 15.12.6. an undervoltage condition also triggers an undervoltage interrupt (see section 15.13). additional actions to shut down t he converter or perform a device reset may also be selected. the internal ldo (ldo13) is also monitor ed for voltage accuracy and fault conditions. an undervoltage condition in ldo13 is indicated us ing the intldo_uv_sts bit. this undervoltage condition also causes an off transition to be scheduled, as described in section 11.3. dc-dc converters 1 and 2 are monitored for overvolt age conditions. an overvolt age condition is set if the voltage is more than 100mv above the required le vel. if an overvoltage condition occurs, then this is indicated using the corresponding st atus bit(s). note that there is no interrupt or other selectable response to an overvoltage condition. the current draw on dc-dc converters 1 and 2 can be monitored agains t user-programmable thresholds in order to detect a high curr ent condition. this f eature is enabled using dc m _hc_ind_ena and the current threshold is set using dc m _hc_thr. note that the high current threshold is not the same as the maximum curr ent capability of the dc-dc converters, but is set according to the application requirements. if a high current condition occurs, then this is indicated using the corresponding status bit(s). a high current condition also triggers a high current interrupt (see section 15.13). 15.12 power management register definitions 15.12.1 dc-dc converter and ldo regulator enable the enable and status register bits for the dc- dc converters and ldo regulators are defined in table 34. address bit label default description r16464 (4050h) dcdc enable 3:0 dc m _ena 0 dc-dc m enable request 0 = disabled 1 = enabled (note that the actual status is indicated in dc m _sts) r16465 (4051h) ldo enable 10:0 ldo n _ena 0 ldo n enable request 0 = disabled 1 = enabled (note that the actual status is indicated in ldo n _sts) r16466 (4052h) dcdc status 3:0 dc m _sts 0 dc-dc m status 0 = disabled 1 = enabled r16467 (4053h) ldo status 10:0 ldo n _sts 0 ldo n status 0 = disabled 1 = enabled notes: 1. n is a number between 1 and 11 that ident ifies the individual ldo regulator. 2. m is a number between 1 and 4 that ident ifies the individual dc-dc converter. table 34 dc-dc converter and ldo regulator control
pre-production WM8310 w pp, may 2012, rev 3.1 75 the enable and status register bits for the exte rnal power enable (epe) controls are defined in table 35. address bit label default description r16464 (4050h) dcdc enable 7 epe2_ena 0 epe2 enable request 0 = disabled 1 = enabled (note that the actual status is indicated in epe2_sts) 6 epe1_ena 0 epe1 enable request 0 = disabled 1 = enabled (note that the actual status is indicated in epe1_sts) r16466 (4052h) dcdc status 7 epe2_sts 0 epe2 status 0 = disabled 1 = enabled 6 epe1_sts 0 epe1 status 0 = disabled 1 = enabled table 35 external power enable (epe) control 15.12.2 dc-dc synchronous buck converter control the register controls for configuring the dc-dc sy nchronous buck converters 1-3 are defined in table 36. note that the dc m _on_slot fields and the 5 msbs of dc m _on_vsel may also be stored in the integrated otp memory. see section 14 for details. address bit label default description r16470 (4056h) dc1 control 1 15:14 dc1_rate [1:0] 10 dc-dc1 voltage ramp rate 00 = 1 step every 32us 01 = 1 step every 16us 10 = 1 step every 8us 11 = immediate voltage change 12 dc1_phase 0 dc-dc1 clock phase control 0 = normal 1 = inverted 9:8 dc1_freq [1:0] 00 dc-dc1 switching frequency 00 = reserved 01 = 2.0mhz 10 = reserved 11 = 4.0mhz 7 dc1_flt 0 dc-dc1 output float 0 = dc-dc1 output discharged when disabled 1 = dc-dc1 output floating when disabled 5:4 dc1_soft_ start [1:0] 00 dc-dc1 soft-start control (duration in each of the 8 startup current limiting steps. 00 = 32us steps 01 = 64us steps 10 = 128us steps 11 = 256us steps
WM8310 pre-production w pp, may 2012, rev 3.1 76 address bit label default description 1:0 dc1_cap 00 dc-dc1 output capacitor 00 = 4.7uf to 20uf 01 = reserved 10 = 22uf to 47uf 11 = reserved r16471 (4057h) dc1 control 2 15:14 dc1_err_a ct [1:0] 00 dc-dc1 error action (undervoltage) 00 = ignore 01 = shut down converter 10 = shut down system (device reset) 11 = reserved note that an interrupt is always raised. 12:11 dc1_hwc_ src [1:0] 00 dc-dc1 hardware control source 00 = disabled 01 = hardware control 1 10 = hardware control 2 11 = hardware control 1 or 2 10 dc1_hwc_ vsel 0 dc-dc1 hardware control voltage select 0 = set by dc1_on_vsel 1 = set by dc1_slp_vsel 9:8 dc1_hwc_ mode [1:0] 11 dc-dc1 hardware control operating mode 00 = forced continuous conduction mode 01 = disabled 10 = ldo mode 11 = hysteretic mode 6:4 dc1_hc_th r [2:0] 000 dc-dc1 high current threshold 000 = 125ma 001 = 250ma 010 = 375ma 011 = 500ma 100 = 625ma 101 = 750ma 110 = 875ma 111 = 1000ma 0 dc1_hc_in d_ena 0 dc-dc1 high current detect enable 0 = disabled 1 = enabled r16472 (4058h) dc1 on config 15:13 dc1_on_sl ot [2:0] 000 dc-dc1 on slot select 000 = do not enable 001 = enable in timeslot 1 010 = enable in timeslot 2 011 = enable in timeslot 3 100 = enable in timeslot 4 101 = enable in timeslot 5 110 = controlled by hardware enable 1 111 = controlled by hardware enable 2
pre-production WM8310 w pp, may 2012, rev 3.1 77 address bit label default description 9:8 dc1_on_m ode [1:0] 00 dc-dc1 on operating mode 00 = forced continuous conduction mode 01 = auto mode (continuous / discontinuous conduction with pulse- skipping) 10 = ldo mode 11 = hysteretic mode 6:2 dc1_on_vs el [6:2] 00000 dc-dc1 on voltage select dc1_on_vsel[6:0] selects the dc- dc1 output voltage from 0.6v to 1.8v in 12.5mv steps. dc1_on_vsel[6:2] also exist in ice/otp memory, controlling the voltage in 50mv steps. dc1_on_vsel[6:0] is coded as follows: 00h to 08h = 0.6v 09h = 0.6125v ? 48h = 1.4v (see note) ? 67h = 1.7875v 68h to 7fh = 1.8v note - maximum output voltage selection in 4mhz switching mode is 48h (1.4v). 1:0 dc1_on_vs el [1:0] 00 r16473 (4059h) dc1 sleep control 15:13 dc1_slp_s lot [2:0] 000 dc-dc1 sleep slot select 000 = sleep voltage / operating mode transition in timeslot 5 001 = disable in timeslot 5 010 = disable in timeslot 4 011 = disable in timeslot 3 100 = disable in timeslot 2 101 = disable in timeslot 1 110 = sleep voltage / operating mode transition in timeslot 3 111 = sleep voltage / operating mode transition in timeslot 1 if dc-dc1 is assigned to a hardware enable input, then codes 001-101 select in which timeslot the converter enters its sleep condition. 9:8 dc1_slp_m ode [1:0] 00 dc-dc1 sleep operating mode 00 = forced continuous conduction mode 01 = auto mode (continuous / discontinuous conduction with pulse- skipping) 10 = ldo mode 11 = hysteretic mode
WM8310 pre-production w pp, may 2012, rev 3.1 78 address bit label default description 6:0 dc1_slp_v sel [6:0] 000_0000 dc-dc1 sleep voltage select 0.6v to 1.8v in 12.5mv steps 00h to 08h = 0.6v 09h = 0.6125v ? 48h = 1.4v (see note) ? 67h = 1.7875v 68h to 7fh = 1.8v note - maximum output voltage selection in 4mhz switching mode is 48h (1.4v). r16474 (405ah) dc1 dvs control 12:11 dc1_dvs_s rc [1:0] 00 dc-dc1 dvs control source 00 = disabled 01 = enabled 10 = controlled by hardware dvs1 11 = controlled by hardware dvs2 6:0 dc1_dvs_v sel [6:0] 000_0000 dc-dc1 dvs voltage select 0.6v to 1.8v in 12.5mv steps 00h to 08h = 0.6v 09h = 0.6125v ? 48h = 1.4v (see note) ? 67h = 1.7875v 68h to 7fh = 1.8v note - maximum output voltage selection in 4mhz switching mode is 48h (1.4v). r16475 (405bh) dc2 control 1 15:14 dc2_rate [1:0] 10 same as dc-dc1 12 dc2_phase 0 same as dc-dc1 9:8 dc2_freq [1:0] 00 same as dc-dc1 7 dc2_flt 0 same as dc-dc1 5:4 dc2_soft_ start [1:0] 00 same as dc-dc1 1:0 dc2_cap 00 same as dc-dc1 r16476 (405ch) dc2 control 2 15:14 dc2_err_a ct [1:0] 00 same as dc-dc1 12:11 dc2_hwc_ src [1:0] 00 same as dc-dc1 10 dc2_hwc_ vsel 0 same as dc-dc1 9:8 dc2_hwc_ mode [1:0] 11 same as dc-dc1 6:4 dc2_hc_th r [2:0] 000 same as dc-dc1 0 dc2_hc_in d_ena 0 same as dc-dc1 r16477 (405dh) dc2 on config 15:13 dc2_on_sl ot [2:0] 000 same as dc-dc1 9:8 dc2_on_m ode [1:0] 00 same as dc-dc1
pre-production WM8310 w pp, may 2012, rev 3.1 79 address bit label default description 6:2 dc2_on_vs el [6:2] 00000 same as dc-dc1 1:0 dc2_on_vs el [1:0] 00 r16478 (405eh) dc2 sleep control 15:13 dc2_slp_s lot [2:0] 000 same as dc-dc1 9:8 dc2_slp_m ode [1:0] 00 same as dc-dc1 6:0 dc2_slp_v sel [6:0] 000_0000 same as dc-dc1 r16479 (405fh) dc2 dvs control 12:11 dc2_dvs_s rc [1:0] 00 same as dc-dc1 6:0 dc2_dvs_v sel [6:0] 000_0000 same as dc-dc1 r16480 (4060h) dc3 control 1 12 dc3_phase 0 same as dc-dc1 7 dc3_flt 0 same as dc-dc1 5:4 dc3_soft_ start [1:0] 01 dc-dc3 soft-start control (duration in each of the 3 intermediate startup current limiting steps.) 00 = immediate start-up 01 = 512us steps 10 = 4.096ms steps 11 = 32.768ms steps 3:2 dc3_stnby _lim [1:0] 01 dc-dc3 current limit sets the maximum dc output current in hysteretic mode. typical values shown below. 00 = 100ma 01 = 200ma 10 = 400ma 11 = 800ma protected by user key. 1:0 dc3_cap 00 dc-dc3 output capacitor 00 = 10uf to 20uf 01 = 10uf to 20uf 10 = 22uf to 45uf 11 = 47uf to 100uf r16481 (4061h) dc3 control 2 15:14 dc3_err_a ct [1:0] 00 same as dc-dc1 12:11 dc3_hwc_ src [1:0] 00 same as dc-dc1 10 dc3_hwc_ vsel 0 same as dc-dc1 9:8 dc3_hwc_ mode [1:0] 11 same as dc-dc1 7 dc3_ovp 0 dc-dc3 overvoltage protection 0 = disabled 1 = enabled r16482 (4062h) dc3 on config 15:13 dc3_on_sl ot [2:0] 000 same as dc-dc1 9:8 dc3_on_m ode [1:0] 00 same as dc-dc1 6:2 dc3_on_vs el [6:2] 00000 dc-dc3 on voltage select
WM8310 pre-production w pp, may 2012, rev 3.1 80 address bit label default description 1:0 dc3_on_vs el [1:0] 00 dc3_on_vsel[6:0] selects the dc- dc3 output voltage from 0.85v to 3.4v in 25mv steps. dc3_on_vsel[6:2] also exist in ice/otp memory, controlling the voltage in 100mv steps. dc3_on_vsel[6:0] is coded as follows: 00h = 0.85v 01h = 0.875v ? 65h = 3.375v 66h to 7fh = 3.4v r16483 (4063h) dc3 sleep control 15:13 dc3_slp_s lot [2:0] 000 same as dc-dc1 9:8 dc3_slp_m ode [1:0] 00 same as dc-dc1 6:0 dc3_slp_v sel [6:0] 000_0000 dc-dc3 sleep voltage select 0.85v to 3.4v in 25mv steps 00h = 0.85v 01h = 0.875v ? 65h = 3.375v 66h to 7fh = 3.4v table 36 dc-dc (buck) converter control 15.12.3 dc-dc boost converter control the register controls for configuring the dc-dc4 boost converter are defined in table 37. note that the dc4_range control register is lock ed by the WM8310 user key. this register can only be changed by writing the appropriate code to the secu rity register, as described in section 12.4 for further details. address bit label default description r16484 (4064h) dc4 control 15:14 dc4_err_a ct [1:0] 00 dc-dc4 error action (undervoltage) 00 = ignore 01 = shut down converter 10 = shut down system (device reset) 11 = reserved note that an interrupt is always raised. 12:11 dc4_hwc_ src[1:0] 00 dc-dc4 hardware control source 00 = disabled 01 = hardware control 1 10 = hardware control 2 11 = hardware control 1 or 2 8 dc4_hwc_ mode 1 dc-dc4 hardware control operating mode 0 = dc-dc4 is controlled by dc4_ena 1 = dc-dc4 is disabled when hardware control source is asserted
pre-production WM8310 w pp, may 2012, rev 3.1 81 address bit label default description 3:2 dc4_rang e[1:0] 01 selects the voltage range for dc-dc4 00 = 20v < vout <= 30v 01 = 10v < vout <= 20v 10 = 6.5v < vout <= 10v 11 = reserved protected by user key 0 dc4_fbsrc 0 dc-dc4 voltage feedback source 0 = isink1 1 = isink2 r16485 (4065h) dc4 sleep control 8 dc4_slpen a 0 dc-dc4 sleep enable 0 = disabled 1 = controlled by dc4_ena table 37 dc-dc (boost) converter control 15.12.4 ldo regulator control the register controls for configuring the ldo regulators 1-6 are defined in table 38. note that the ldo n _on_slot and ldo n _on_vsel fields may also be stored in the integrated otp memory. see section 14 for details. address bit label default description r16488 (4068h) ldo1 control 15:14 ldo1_err_ act [1:0] 00 ldo1 error action (undervoltage) 00 = ignore 01 = shut down regulator 10 = shut down system (device reset) 11 = reserved note that an interrupt is always raised. 12:11 ldo1_hwc _src [1:0] 00 ldo1 hardware control source 00 = disabled 01 = hardware control 1 10 = hardware control 2 11 = hardware control 1 or 2 10 ldo1_hwc _vsel 0 ldo1 hardware control voltage select 0 = set by ldo1_on_vsel 1 = set by ldo1_slp_vsel 9:8 ldo1_hwc _mode 10 ldo1 hardware control operating mode 00 = low power mode 01 = turn converter off 10 = low power mode 11 = set by ldo1_on_mode 7 ldo1_flt 0 ldo1 output float 0 = ldo1 output discharged when disabled 1 = ldo1 output floating when disabled 6 ldo1_swi 0 ldo1 switch mode 0 = ldo mode 1 = switch mode 0 ldo1_lp_m ode 0 ldo1 low power mode select 0 = 50ma (reduced quiescent current) 1 = 20ma (minimum quiescent current) selects which low power mode is used in on, sleep, or under hwc modes.
WM8310 pre-production w pp, may 2012, rev 3.1 82 address bit label default description r16489 (4069h) ldo1 on control 15:13 ldo1_on_s lot [2:0] 000 ldo1 on slot select 000 = do not enable 001 = enable in timeslot 1 010 = enable in timeslot 2 011 = enable in timeslot 3 100 = enable in timeslot 4 101 = enable in timeslot 5 110 = controlled by hardware enable 1 111 = controlled by hardware enable 2 8 ldo1_on_ mode 0 ldo1 on operating mode 0 = normal mode 1 = low power mode 4:0 ldo1_on_v sel [4:0] 00000 ldo1 on voltage select 0.9v to 1.6v in 50mv steps 1.7v to 3.3v in 100mv steps 00h = 0.90v 01h = 0.95v ? 0eh = 1.60v 0fh = 1.70v ? 1eh = 3.20v 1fh = 3.30v r16490 (406ah) ldo1 sleep control 15:13 ldo1_slp_ slot [2:0] 000 ldo1 sleep slot select 000 = sleep voltage / operating mode transition in timeslot 5 001 = disable in timeslot 5 010 = disable in timeslot 4 011 = disable in timeslot 3 100 = disable in timeslot 2 101 = disable in timeslot 1 110 = sleep voltage / operating mode transition in timeslot 3 111 = sleep voltage / operating mode transition in timeslot 1 if ldo1 is assigned to a hardware enable input, then codes 001-101 select in which timeslot the regulator enters its sleep condition. 8 ldo1_slp_ mode 0 ldo1 sleep operating mode 0 = normal mode 1 = low power mode 4:0 ldo1_slp_ vsel [4:0] 00000 ldo1 sleep voltage select 0.9v to 1.6v in 50mv steps 1.7v to 3.3v in 100mv steps 00h = 0.90v 01h = 0.95v ? 0eh = 1.60v 0fh = 1.70v ? 1eh = 3.20v 1fh = 3.30v r16491 (406bh) 15:14 ldo2_err_ act [1:0] 00 same as ldo1
pre-production WM8310 w pp, may 2012, rev 3.1 83 address bit label default description ldo2 control 12:11 ldo2_hwc _src [1:0] 00 same as ldo1 10 ldo2_hwc _vsel 0 same as ldo1 9:8 ldo2_hwc _mode 10 same as ldo1 7 ldo2_flt 0 same as ldo1 6 ldo2_swi 0 same as ldo1 0 ldo2_lp_m ode 0 same as ldo1 r16492 (406ch) ldo2 on control 15:13 ldo2_on_s lot [2:0] 000 same as ldo1 8 ldo2_on_ mode 0 same as ldo1 4:0 ldo2_on_v sel [4:0] 00000 same as ldo1 r16493 (406dh) ldo2 sleep control 15:13 ldo2_slp_ slot [2:0] 000 same as ldo1 8 ldo2_slp_ mode 0 same as ldo1 4:0 ldo2_slp_ vsel [4:0] 00000 same as ldo1 r16494 (406eh) ldo3 control 15:14 ldo3_err_ act [1:0] 00 same as ldo1 12:11 ldo3_hwc _src [1:0] 00 same as ldo1 10 ldo3_hwc _vsel 0 same as ldo1 9:8 ldo3_hwc _mode 10 same as ldo1 7 ldo3_flt 0 same as ldo1 6 ldo3_swi 0 same as ldo1 0 ldo3_lp_m ode 0 same as ldo1 r16495 (406fh) ldo3 on control 15:13 ldo3_on_s lot [2:0] 000 same as ldo1 8 ldo3_on_ mode 0 same as ldo1 4:0 ldo3_on_v sel [4:0] 00000 same as ldo1 r16496 (4070h) ldo3 sleep control 15:13 ldo3_slp_ slot [2:0] 000 same as ldo1 8 ldo3_slp_ mode 0 same as ldo1 4:0 ldo3_slp_ vsel [4:0] 00000 same as ldo1 r16497 (4071h) ldo4 control 15:14 ldo4_err_ act [1:0] 00 same as ldo1 12:11 ldo4_hwc _src [1:0] 00 same as ldo1 10 ldo4_hwc _vsel 0 same as ldo1 9:8 ldo4_hwc _mode 10 same as ldo1 7 ldo4_flt 0 same as ldo1 6 ldo4_swi 0 same as ldo1
WM8310 pre-production w pp, may 2012, rev 3.1 84 address bit label default description 0 ldo4_lp_m ode 0 same as ldo1 r16498 (4072h) ldo4 on control 15:13 ldo4_on_s lot [2:0] 000 same as ldo1 8 ldo4_on_ mode 0 same as ldo1 4:0 ldo4_on_v sel [4:0] 00000 same as ldo1 r16499 (4073h) ldo4 sleep control 15:13 ldo4_slp_ slot [2:0] 000 same as ldo1 8 ldo4_slp_ mode 0 same as ldo1 4:0 ldo4_slp_ vsel [4:0] 00000 same as ldo1 r16500 (4074h) ldo5 control 15:14 ldo5_err_ act [1:0] 00 same as ldo1 12:11 ldo5_hwc _src [1:0] 00 same as ldo1 10 ldo5_hwc _vsel 0 same as ldo1 9:8 ldo5_hwc _mode 10 same as ldo1 7 ldo5_flt 0 same as ldo1 6 ldo5_swi 0 same as ldo1 0 ldo5_lp_m ode 0 same as ldo1 r16501 (4075h) ldo5 on control 15:13 ldo5_on_s lot [2:0] 000 same as ldo1 8 ldo5_on_ mode 0 same as ldo1 4:0 ldo5_on_v sel [4:0] 00000 same as ldo1 r16502 (4076h) ldo5 sleep control 15:13 ldo5_slp_ slot [2:0] 000 same as ldo1 8 ldo5_slp_ mode 0 same as ldo1 4:0 ldo5_slp_ vsel [4:0] 00000 same as ldo1 r16503 (4077h) ldo6 control 15:14 ldo6_err_ act [1:0] 00 same as ldo1 12:11 ldo6_hwc _src [1:0] 00 same as ldo1 10 ldo6_hwc _vsel 0 same as ldo1 9:8 ldo6_hwc _mode 10 same as ldo1 7 ldo6_flt 0 same as ldo1 6 ldo6_swi 0 same as ldo1 0 ldo6_lp_m ode 0 same as ldo1 r16504 (4078h) ldo6 on control 15:13 ldo6_on_s lot [2:0] 000 same as ldo1 8 ldo6_on_ mode 0 same as ldo1 4:0 ldo6_on_v sel [4:0] 00000 same as ldo1
pre-production WM8310 w pp, may 2012, rev 3.1 85 address bit label default description r16505 (4079h) ldo6 sleep control 15:13 ldo6_slp_ slot [2:0] 000 same as ldo1 8 ldo6_slp_ mode 0 same as ldo1 4:0 ldo6_slp_ vsel [4:0] 00000 same as ldo1 table 38 ldo regulators 1-6 control the register controls for configuring the ldo regulators 7-10 are defined in table 39. note that the ldo n _on_slot and ldo n _on_vsel fields may also be stored in the integrated otp memory. see section 14 for details. address bit label default description r16506 (407ah) ldo7 control 15:14 ldo7_err_ act [1:0] 00 ldo7 error action (undervoltage) 00 = ignore 01 = shut down regulator 10 = shut down system (device reset) 11 = reserved note that an interrupt is always raised. 12:11 ldo7_hwc _src [1:0] 00 ldo7 hardware control source 00 = disabled 01 = hardware control 1 10 = hardware control 2 11 = hardware control 1 or 2 10 ldo7_hwc _vsel 0 ldo7 hardware control voltage select 0 = set by ldo7_on_vsel 1 = set by ldo7_slp_vsel 9:8 ldo7_hwc _mode 00 ldo7 hardware control operating mode 00 = low power mode 01 = turn converter off 10 = low power mode 11 = set by ldo7_on_mode 7 ldo7_flt 0 ldo7 output float 0 = ldo7 output discharged when disabled 1 = ldo7 output floating when disabled 6 ldo7_swi 0 ldo7 switch mode 0 = ldo mode 1 = switch mode r16507 (407bh) ldo7 on control 15:13 ldo7_on_s lot [2:0] 000 ldo7 on slot select 000 = do not enable 001 = enable in timeslot 1 010 = enable in timeslot 2 011 = enable in timeslot 3 100 = enable in timeslot 4 101 = enable in timeslot 5 110 = controlled by hardware enable 1 111 = controlled by hardware enable 2 8 ldo7_on_ mode 0 ldo7 on operating mode 0 = normal mode 1 = low power mode
WM8310 pre-production w pp, may 2012, rev 3.1 86 address bit label default description 4:0 ldo7_on_v sel [4:0] 00000 ldo7 on voltage select 1.0v to 1.6v in 50mv steps 1.7v to 3.5v in 100mv steps 00h = 1.00v 01h = 1.05v 02h = 1.10v ? 0ch = 1.60v 0dh = 1.70v ? 1eh = 3.40v 1fh = 3.50v r16508 (407ch) ldo7 sleep control 15:13 ldo7_slp_ slot [2:0] 000 ldo7 sleep slot select 000 = sleep voltage / operating mode transition in timeslot 5 001 = disable in timeslot 5 010 = disable in timeslot 4 011 = disable in timeslot 3 100 = disable in timeslot 2 101 = disable in timeslot 1 110 = sleep voltage / operating mode transition in timeslot 3 111 = sleep voltage / operating mode transition in timeslot 1 if ldo7 is assigned to a hardware enable input, then codes 001-101 select in which timeslot the regulator enters its sleep condition. 8 ldo7_slp_ mode 0 ldo7 sleep operating mode 0 = normal mode 1 = low power mode 4:0 ldo7_slp_ vsel [4:0] 00000 ldo7 sleep voltage select 1.0v to 1.6v in 50mv steps 1.7v to 3.5v in 100mv steps 00h = 1.00v 01h = 1.05v 02h = 1.10v ? 0ch = 1.60v 0dh = 1.70v ? 1eh = 3.40v 1fh = 3.50v r16509 (407dh) ldo8 control 15:14 ldo8_err_ act [1:0] 00 same as ldo7 12:11 ldo8_hwc _src [1:0] 00 same as ldo7 10 ldo8_hwc _vsel 0 same as ldo7 9:8 ldo8_hwc _mode 00 same as ldo7 7 ldo8_flt 0 same as ldo7 6 ldo8_swi 0 same as ldo7 r16510 (407eh) 15:13 ldo8_on_s lot [2:0] 000 same as ldo7
pre-production WM8310 w pp, may 2012, rev 3.1 87 address bit label default description ldo8 on control 8 ldo8_on_ mode 0 same as ldo7 4:0 ldo8_on_v sel [4:0] 00000 same as ldo7 r16511 (407fh) ldo8 sleep control 15:13 ldo8_slp_ slot [2:0] 000 same as ldo7 8 ldo8_slp_ mode 0 same as ldo7 4:0 ldo8_slp_ vsel [4:0] 00000 same as ldo7 r16512 (4080h) ldo9 control 15:14 ldo9_err_ act [1:0] 00 same as ldo7 12:11 ldo9_hwc _src [1:0] 00 same as ldo7 10 ldo9_hwc _vsel 0 same as ldo7 9:8 ldo9_hwc _mode 00 same as ldo7 7 ldo9_flt 0 same as ldo7 6 ldo9_swi 0 same as ldo7 r16513 (4081h) ldo9 on control 15:13 ldo9_on_s lot [2:0] 000 same as ldo7 8 ldo9_on_ mode 0 same as ldo7 4:0 ldo9_on_v sel [4:0] 00000 same as ldo7 r16514 (4082h) ldo9 sleep control 15:13 ldo9_slp_ slot [2:0] 000 same as ldo7 8 ldo9_slp_ mode 0 same as ldo7 4:0 ldo9_slp_ vsel [4:0] 00000 same as ldo7 r16515 (4083h) ldo10 control 15:14 ldo10_err _act [1:0] 00 same as ldo7 12:11 ldo10_hw c_src [1:0] 00 same as ldo7 10 ldo10_hw c_vsel 0 same as ldo7 9:8 ldo10_hw c_mode 00 same as ldo7 7 ldo10_flt 0 same as ldo7 6 ldo10_swi 0 same as ldo7 r16516 (4084h) ldo10 on control 15:13 ldo10_on_ slot [2:0] 000 same as ldo7 8 ldo10_on_ mode 0 same as ldo7 4:0 ldo10_on_ vsel [4:0] 00000 same as ldo7 r16517 (4085h) ldo10 sleep control 15:13 ldo10_slp _slot [2:0] 000 same as ldo7 8 ldo10_slp _mode 0 same as ldo7 4:0 ldo10_slp _vsel [4:0] 00000 same as ldo7 table 39 ldo regulators 7-10 control
WM8310 pre-production w pp, may 2012, rev 3.1 88 the register controls for configuring t he ldo regulator 11 are defined in table 40. note that the ldo11_on_slot and ldo11_on_vsel fields may also be stored in the integrated otp memory. see section 14 for details. address bit label default description r16519 (4087h) ldo11 on control 15:13 ldo11_on_ slot [2:0] 000 ldo11 on slot select 000 = do not enable 001 = enable in timeslot 1 010 = enable in timeslot 2 011 = enable in timeslot 3 100 = enable in timeslot 4 101 = enable in timeslot 5 110 = controlled by hardware enable 1 111 = controlled by hardware enable 2 12 ldo11_frc ena 0 ldo11 force enable (forces ldo11 to be enabled at all times in the off, on and sleep states) 0 = disabled 1 = enabled 7 ldo11_vse l_src 0 ldo11 voltage select source 0 = normal (ldo11 settings) 1 = same as dc-dc converter 1 3:0 ldo11_on_ vsel [3:0] ldo11 on voltage select 0.80v to 1.55v in 50mv steps 0h = 0.80v 1h = 0.85v 2h = 0.90v ? eh = 1.50v fh = 1.55v r16520 (4088h) ldo11 sleep control 15:13 ldo11_slp _slot [2:0] 000 ldo11 sleep slot select 000 = sleep voltage / operating mode transition in timeslot 5 001 = disable in timeslot 5 010 = disable in timeslot 4 011 = disable in timeslot 3 100 = disable in timeslot 2 101 = disable in timeslot 1 110 = sleep voltage / operating mode transition in timeslot 3 111 = sleep voltage / operating mode transition in timeslot 1 if ldo11 is assigned to a hardware enable input, then codes 001-101 select in which timeslot the regulator enters its sleep condition. 3:0 ldo11_slp _vsel [3:0] ldo11 sleep voltage select 0.80v to 1.55v in 50mv steps 0h = 0.80v 1h = 0.85v 2h = 0.90v ? eh = 1.50v fh = 1.55v table 40 ldo regulator 11 control
pre-production WM8310 w pp, may 2012, rev 3.1 89 15.12.5 external power enable (epe) control the register controls for configuring the exter nal power enable (epe) outputs are defined in table 41. note that the epe1_on_slot and epe2_on_slot fiel ds may also be stored in the integrated otp memory. see section 14 for details. address bit label default description r16486 (4066h) epe1 control 15:13 epe1_on_s lot [2:0] 000 epe1 on slot select 000 = do not enable 001 = enable in timeslot 1 010 = enable in timeslot 2 011 = enable in timeslot 3 100 = enable in timeslot 4 101 = enable in timeslot 5 110 = controlled by hardware enable 1 111 = controlled by hardware enable 2 12:11 epe1_hwc _src [1:0] 00 epe1 hardware control source 00 = disabled 01 = hardware control 1 10 = hardware control 2 11 = hardware control 1 or 2 8 epe1_hwc ena 0 epe1 hardware control enable 0 = epe1 is controlled by epe1_ena (hardware control input(s) are ignored) 1 = epe1 is controlled by hwc inputs (hardware control input(s) force epe1 to be de-asserted) 7:5 epe1_slp_ slot [2:0] 000 epe1 sleep slot select 000 = no action 001 = disable in timeslot 5 010 = disable in timeslot 4 011 = disable in timeslot 3 100 = disable in timeslot 2 101 = disable in timeslot 1 110 = no action 111 = no action r16487 (4067h) epe2 control 15:13 epe2_on_s lot [2:0] 000 same as epe1 12:11 epe2_hwc _src [1:0] 00 same as epe1 8 epe2_hwc ena 0 same as epe1 7:5 epe2_slp_ slot [2:0] 000 same as epe1 table 41 external power enable (epe) control 15.12.6 monitoring and fault reporting the overvoltage, undervoltage and high current st atus registers are defined in table 42. address bit label default description r16468 (4054h) dcdc uv status 13 dc2_ov_st s 0 dc-dc2 overvoltage status 0 = normal 1 = overvoltage 12 dc1_ov_st s 0 dc-dc1 overvoltage status 0 = normal 1 = overvoltage
WM8310 pre-production w pp, may 2012, rev 3.1 90 address bit label default description 9 dc2_hc_st s 0 dc-dc2 high current status 0 = normal 1 = high current 8 dc1_hc_st s 0 dc-dc1 high current status 0 = normal 1 = high current 3:0 dc m _uv_s ts 0 dc-dc m undervoltage status 0 = normal 1 = undervoltage r16469 (4055h) ldo uv status 15 intldo_uv _sts 0 ldo13 (internal ldo) undervoltage status 0 = normal 1 = undervoltage 9:0 ldo n _uv_s ts 0 ldo n undervoltage status 0 = normal 1 = undervoltage notes: 1. n is a number between 1 and 10 that identifies the individual ldo regulator (ldo1 - 10). 2. m is a number between 1 and 4 that identifies the individual dc-dc converter (dc-dc1 - 4). table 42 dc converter and ldo regulator status 15.13 power management interrupts undervoltage monitoring is provided on all dc-dc c onverters and ldo regulators, as described in section 15.11. the associated interrupt flags i ndicate an undervoltage condi tion in each individual dc-dc converter or ldo regulator. each of these secondary interrupts triggers a primary undervoltage interrupt, uv_int (see section 23). th is can be masked by setting the mask bit(s) as described in table 43. current monitoring is provided on dc-dc1 and dc-dc2, as described in section 15.11. the interrupt flags hc_dc1_eint and hc_dc2_eint indicate a high current condition in dc-dc1 and dc-dc2 respectively. each of these secondary interrupts triggers a primary high current interrupt, hc_int (see section 23). this can be masked by setting the mask bit(s) as described in table 43. the high current thresholds are programmable; these are set by dc1_hc_thr and dc2_hc_thr for dc-dc1 and dc-dc2 respectively. see section 15.12. 2 for details of these register fields. note that these functions are for current monitoring; they do not equate to the dc-dc converter maximum current limit. address bit label description r16403 (4013h) interrupt status 3 9:0 uv_ldo n _eint ldo n undervoltage interrupt (rising edge triggered) note: cleared when a ?1? is written. r16404 (4014h) interrupt status 4 9 hc_dc2_eint dc-dc2 high current interrupt (rising edge triggered) note: cleared when a ?1? is written. 8 hc_dc1_eint dc-dc1 high current interrupt (rising edge triggered) note: cleared when a ?1? is written. 3:0 uv_dc m _eint dc-dc m undervoltage interrupt (rising edge triggered) note: cleared when a ?1? is written. r16411 (401bh) interrupt status 3 mask 9:0 im_uv_ldo n _eint interrupt mask. 0 = do not mask interrupt. 1 = mask interrupt.
pre-production WM8310 w pp, may 2012, rev 3.1 91 address bit label description default value is 1 (masked) r16412 (401ch) interrupt status 4 mask 9 im_hc_dc2_eint interrupt mask. 0 = do not mask interrupt. 1 = mask interrupt. default value is 1 (masked) 8 im_hc_dc1_eint interrupt mask. 0 = do not mask interrupt. 1 = mask interrupt. default value is 1 (masked) 3:0 im_uv_dc m _eint interrupt mask. 0 = do not mask interrupt. 1 = mask interrupt. default value is 1 (masked) notes: 1. n is a number between 1 and 10 that identifies the individual ldo regulator (ldo1 - 10). 2. m is a number between 1 and 4 that identifies the individual dc-dc converter (dc-dc1 - 4). table 43 power management interrupts 15.14 power good indication the WM8310 can indicate the status of the dc-dc converters and ldo regulators via a gpio pin configured as a ?pwr_good? output (see section 21). each dc-dc converter and ldo regulator to be moni tored in this way must be individually enabled as an input to the pwr_good function using the register bits defined in table 44. when a gpio pin is configured as a ?pwr_good? output, this signal is asserted when all selected dc-dc converters and ldo regulators are operating correctly. if any of the enabled dc-dc converters or ldo regulators is undervoltage, then the pwr_good will be de-asserted. in this event, the host processor should read the undervo ltage interrupt fields to determine which dc-dc converter or ldo regulator is affected. note that an undervoltage condition may lead to a c onverter being switched off automatically. in this case, the disabled converter will not indicate t he fault condition via pwr_ good. accordingly, the pwr_good signal may not be a reliable output in cases where the WM8310 is configured to shut down any converters automatically under undervo ltage conditions. it is recommended that the host processor should read the undervoltage interrupts in response to pwr_good being de-asserted. the host processor can then initiate the most appropriate response. address bit label default description r16526 (408eh) power good source 1 3 dc4_ok 0 dc-dc4 status selected as an input to pwr_good 0 = disabled 1 = enabled 2 dc3_ok 1 dc-dc3 status selected as an input to pwr_good 0 = disabled 1 = enabled 1 dc2_ok 1 dc-dc2 status selected as an input to pwr_good 0 = disabled 1 = enabled 0 dc1_ok 1 dc-dc1 status selected as an input to pwr_good 0 = disabled 1 = enabled r16527 (408fh) 9 ldo10_ok 1 ldo10 status selected as an input to pwr_good
WM8310 pre-production w pp, may 2012, rev 3.1 92 address bit label default description power good source 2 0 = disabled 1 = enabled 8 ldo9_ok 1 ldo9 status selected as an input to pwr_good 0 = disabled 1 = enabled 7 ldo8_ok 1 ldo8 status selected as an input to pwr_good 0 = disabled 1 = enabled 6 ldo7_ok 1 ldo7 status selected as an input to pwr_good 0 = disabled 1 = enabled 5 ldo6_ok 1 ldo6 status selected as an input to pwr_good 0 = disabled 1 = enabled 4 ldo5_ok 1 ldo5 status selected as an input to pwr_good 0 = disabled 1 = enabled 3 ldo4_ok 1 ldo4 status selected as an input to pwr_good 0 = disabled 1 = enabled 2 ldo3_ok 1 ldo3 status selected as an input to pwr_good 0 = disabled 1 = enabled 1 ldo2_ok 1 ldo2 status selected as an input to pwr_good 0 = disabled 1 = enabled 0 ldo1_ok 1 ldo1 status selected as an input to pwr_good 0 = disabled 1 = enabled table 44 pwr_good (gpio) configuration 15.15 dc-dc converter operation 15.15.1 overview the WM8310 provides four dc-dc switching converte rs. three of these are synchronous buck (step- down) converters; the fourth of t hese is a boost (step-up) converter. the principal characteristics of each dc-dc converter are shown below. dc-dc1 / dc-dc2 dc-dc3 dc-dc4 converter type buck (step-down) buck (step-down) boost (step-up) input voltage range 2.7v to 5.5v (connect to sysvdd supply) output voltage range 0.6v to 1.8v 0.85v to 3.4v 5v to 30v load current rating up to 1200ma up to 1000ma up to 25ma @ 30v up to 40ma @ 20v up to 90ma @ 8v switching frequency 2mhz or 4mhz 2mhz 1mhz table 45 dc-dc converter overview
pre-production WM8310 w pp, may 2012, rev 3.1 93 15.15.2 dc-dc synchronous buck converters dc-dc converters 1, 2 and 3 are synchronous buck converters which deliv er high performance and high efficiency across a wide va riety of operating conditions. the high switching frequency, together with the cu rrent mode architecture, delivers exceptional transient performance suitable for supplying proc essor power domains and similar applications requiring high stability through fast -changing load (or li ne) conditions. the current mode architecture enables extended bandwidth of the control loop, allowing the dc-dc converter to adapt for changes in input or output conditions more rapidly than can be achieved using other feedback mechanisms. this improves t he converter?s performanc e under transient load conditions. the flexible design of the dc-dc converters allows a selection of different operating configurations, which can be chosen according to the performance, efficiency, space or external component cost requirements. the dc-dc converter design achiev es high performance with a sma ll inductor component. this is highly advantageous in size-critical designs for portable applications . in the case of dc-dc1 and dc- dc2, the switching frequency is selectable (2mh z or 4mhz). the higher frequency supports best transient performance and the smallest external i nductor, whilst the lower rate supports best power efficiency. it should be noted that the supported output voltage range is restricted in the 4mhz mode; for output voltages greater than 1.4v, the 2mhz mode must be used. the dc-dc converters are compatible with a range of external output capacitors. a larger capacitor (eg. 47 ? f) will deliver best transient performance, whilst a smaller capacitor (eg. 4.7 ? f) may be preferred for size or cost reasons. four different operating modes can be selected, allowing the user to configure the converter performance and efficiency according to different demands. this includes power-saving modes for light load conditions and a high per formance mode for best transient load performance. a low power ldo regulator mode is also provided. the dc-dc converters maintain output voltage regulation when switching between operating modes. forced continuous conduction mode (fccm) this mode delivers the best load transient perform ance across the entire operating load range of the converter. it also provides the best emi characteristics due to the fixed, regular switching pattern. for normal dc-dc buck converter operation, ther e is an inductor charging phase followed by a discharging phase. under light l oad conditions, the inductor curr ent may be positive or negative during this cycle. (note that the load current corresponds to the average inductor current.) the negative portion of the cycle corresponds to inefficient operation, as the output capacitor is discharged unnecessarily by the conver ter circuit. accordingly, this m ode is not optimally efficient for light load conditions. this mode offers excellent performance under trans ient load conditions. it exceeds the performance of the other operating modes in the event of a decreasing current demand or a decreasing voltage selection. this is because fccm mode can actively pull down the output voltage to the required level, whilst other modes rely on the load to pull t he converter voltage down under these conditions. another important benefit of this mode is that t he switching pattern is fixed, regardless of load conditions. this provides best compatibility with noise-sensitiv e circuits where the noise frequency spectrum must be well-defined. although this mode is not optimally efficient for light loads, it delivers the bes t possible transient load performance and fixed frequency switching. this mode should be selected when best performance is required, delivering minimum output voltage ripple across all static or tr ansient load conditions.
WM8310 pre-production w pp, may 2012, rev 3.1 94 auto mode: continuous / discontinuous conducti on with pulse-skipping (ccm/dcm with ps) this is an automatic mode that selects different control modes according to the load conditions. the converter supports the full range of load conditions in this mode, and automatically selects power- saving mechanisms when the load conditions are suit able. under light load c onditions, the efficiency in this mode is superior to the fccm mode. t he transient load performanc e may be slightly worse than fccm mode. the converter operates in continuous conduc tion mode (ccm) for heav y load conditions, and discontinuous conduction mode (dcm ) under lighter loads. discont inuous conduction is when the inductor current falls to zero during the dischar ge phase, and the converter disables the synchronous rectifier transistor in order that the inductor cu rrent remains at zero until the next charge phase. negative inductor current is blocked in this mode, eliminating the associated losses, and improving efficiency. the transient response in this mode varies accordi ng to the operating conditions ; it differs from fccm in the case of a decreasing current demand or a decr easing voltage, as the conv erter uses the load to pull the output voltage down to the required level. a light load will result in a slow response time. a minimum inductor charge time is applied in dcm mode; this leads to a minimum average inductor current when operating as described above. under ve ry light load conditions , pulse skipping is used to reduce the average inductor current to the level required by the load. in pulse-skipping mode, the charge phase of selected cycles is not scheduled, and the load is supported by the output capacitor over more than one cycle of the switching frequency. as well as supporting very light load current conditions, this mechanism offers power savings, as the switching losses associated with the skipped pulses are eliminated. a disadvantage of this is that the transient response is degraded even further with respect to dcm. when the pulse-skipping behav iour is invoked, an increased output voltage ripple may be observed under some load conditions. this mode is suitable for a wide range of operat ing conditions. it supports the full range of load currents, and offers efficiency sa vings under light load conditions. hysteretic mode hysteretic mode is a power-saving mode. it does not support the full load capability of the dc-dc converter, but offers efficiency improvements over the fccm and auto (ccm/dcm with ps) modes. the control circuit in hysteretic mode operates very differently to the pulse-skipping mode that is available in auto mode. in pulse-skipping mode, selected switching cycles are dropped in order to reduce the output current to match a light load c ondition, whilst maintaining good output voltage ripple as far as possible. in hysteretic mode, t he converter uses swit ched operation on an adaptive intermittent basis to deliver the required average current to the load. in the switched operation portion of the hysteretic mode, the converter drives the output voltage up; this is followed by a power-saving period in which t he control circuit is lar gely disabled whilst the load pulls the output voltage down again over a period of m any switching cycles. the duration of the fixed frequency bursts and the time between bursts is adapted automatically by the output voltage monitoring circuit. in this mode, the power dissipation is reduced to a very low level by disabling parts of the control circuitry for the duration of selected switching cycles . this improves the overall efficiency, but also leads to output voltage ripple and limited performanc e. this mode produces a larger output voltage ripple than the pulse-skipping mode. in order to limit the degradation of the dc-dc converter performance in hysteretic mode, the control ci rcuit is designed for a restricted range of load conditions only. note that the irregular switch ing pattern also results in degraded emi behaviour. hysteretic mode and pulse skipping mode are bot h pulse frequency modulation (pfm)-type modes, where the switching pulse frequency is adjusted dynam ically according to the load requirements. a consequence of this frequency m odulation is that the circuit?s emi characteristics are less predictable. in hysteretic mode in particular, the emi effects arising from the dc-dc switching are present across a wider frequency band than is the case in ccm and dcm. it is more difficult to effectively suppress the wide band interference, and this factor may resu lt in hysteretic mode being unsuitable for some operating conditions.
pre-production WM8310 w pp, may 2012, rev 3.1 95 hysteretic mode is suitable for light load conditi ons only, and only suitable for operating modes that are not sensitive to wide band rf/emi effects. the output voltage ripple (and frequency) is load dependent, and is generally worse than pulse-skipping oper ation in the auto mode. provided that the emi and voltage ripple can be tolerated, the hyster etic mode offers an effi ciency advantage over the auto (ccm/dcm with ps) mode. ldo mode in this mode, there is no fet switching at all, and the converter operates as a low drop-out (ldo) regulator. in this mode, the fet switching losses ar e eliminated, as is the power consumption of the dc-dc control circuit. under suitable operating conditions, this provides the most efficient option for light loads, without any of the emi or volt age ripple limitations of hysteretic mode. as with any ldo, the output voltage is constant, and there is no internal source of voltage ripple. unlike the switching modes, the power efficienc y of the ldo mode is highly dependent on the input and output voltages; the ldo is most efficient when the voltage drop between input and output is small. the power dissipated as heat loss by an ldo increases rapidly as the input - output voltage difference increases. ldo mode is suitable for light l oads, and provides a ripple-free outpu t. the ldo mode features a very low start-up current; this mode can be used to avoid the higher in-rush current that occurs in the switching converter modes. the efficiency is dependent on the input - output voltage configuration; the ldo mode can be highly efficient, but may also be unacceptably inefficient. if an improvement in power efficiency is required, then hysteretic mode may be the preferred choice or, for better emi and voltage ripple, the auto (ccm/dcm with ps) mode may be the optimum selection. operating mode summary mode description application forced continuous conduction mode (fccm) buck converter operation where inductor current is continuous at all times. high performance for all static and transient load conditions. fix ed frequency switching offers best compatibility with sensitive circuits. auto mode: continuous / discontinuous conduction with pulse-skipping mode (ccm/dcm with ps) buck converter operation where inductor current may be discontinuous under reduced loads; pulse-skipping also enabled under lighter loads. high efficiency for all static and transient load conditions. performance may be less than fccm mode for heavy load transients. hysteretic mode the converter uses a hysteretic control scheme with pulsed switching operation. the control circuitry is dis abled intermittently for power saving. high efficiency for light static and light transient loads only. ma ximum load current is restricted; output voltage ripple is increased. ldo mode no fet switching at all; linear regulator operation. power saving mode for light loads only. high efficiency for ultra light loads. low current soft-start control. table 46 dc-dc synchronous buck converter operating modes summary typical connections the typical connections to dc-dc converter 1 are illustrated in figure 20. the equivalent circuit applies to dc-dc converters 2 and 3 also. the input voltage connection to dc-dc converters 1, 2 and 3 is provided on dc1vdd, dc2vdd and dc3vdd respectively; these are typically connec ted to the sysvdd voltage node. note that the internal supply pins pvdd1 and pvdd2 must be connected to the same supply voltage as the dc- dc converters (ie. sysvdd).
WM8310 pre-production w pp, may 2012, rev 3.1 96 figure 20 dc-dc synchronous buck converter connections the recommended output capacitor c out varies according to the requi red transient response. note that the dc m _cap register field must be set accord ing to the output capacitance on each dc-dc converter in order to achieve best performance. in the case of dc-dc1 and dc-dc2, the recommended inductor component varies according to the dc m _freq register field. this r egister supports a choice of different switching frequencies. see section 30.3 for details of spec ific recommended external components. 15.15.3 dc-dc step up converter dc-dc converter 4 is a step-up dc-dc converter des igned to deliver high power efficiency across full load conditions. it is designed to provide a voltage which is determined by the selected current of either current sink 1 or current sink 2 thr ough an external load - typically a string of leds. dc-dc converter 4 is designed with fixed frequency current mode ar chitecture. the clock frequency is set by an internal rc oscillator, which provides a 1mhz clock. the typical connections to dc-dc converter 4 are illustrated in figure 21. the dc4_fbsrc register field can select either isink1 or is ink2 as input to the feedback circuit. the input voltage connection, dc4vdd, is typica lly connected to the sysvdd voltage node. note that the internal supply pins pvdd1 and pvdd2 should also be connected to sysvdd.
pre-production WM8310 w pp, may 2012, rev 3.1 97 figure 21 dc-dc boost converter connections note that the recommended output capacitor c out varies according to the required output voltage. the dc4_range register field must be set according to the required output voltage. see section 30.4 for details of spec ific recommended external components. 15.16 ldo regulator operation 15.16.1 overview the WM8310 provides 11 ldo regulators. four of these are low-noise analogue ldos. one of the ldo regulators (ldo11) can be configured to be enabled even when the WM8310 is in the off state. the principal characteristics of the ldo regulators are shown below. ldo1 ldo2, 3 ldo4, 5, 6 ldo7, 8 ldo9, 10 ldo11 converter type general purpose general purpose general purpose analogue analogue general purpose input voltage range 1.5v to 5.5v (must be sysvdd voltage) 1.71v to 5.5v 1.8v to 5.5v output voltage range 0.9v to 3.3v 0.9v to 3.3v 0.9v to 3.3v 1.0v to 3.5v 1.0v to 3.5v 0.8v to 1.55v load current rating up to 300ma up to 200ma up to 100ma up to 200ma up to 150ma up to 25ma pass device impedance @ 2.5v 1 ? 1 ? 2 ? 1 ? 2 ? n/a table 47 ldo regulator overview 15.16.2 ldo regulators the ldo regulators are configurabl e circuits which generate accurate , low-noise supply voltages for various system components. the ldo regulator s are dynamically programmable and can be re- configured at any time. two low power modes ar e provided for the general purpose ldos 1-6; a single low power mode is provided for the analogue ld os 7-10; this enables the overall device power consumption to be minimised at all times.
WM8310 pre-production w pp, may 2012, rev 3.1 98 the ldos 1-10 can also operate as current-limited swit ches, with no voltage regulation; this is useful for ?hot swap? outputs, i.e. supply rails for exter nal devices that are plugged in when the system is already powered up - the current-limiting function prev ents the in-rush current into the external device from disturbing other system power supplies. the input voltage to these ldos is provided on pin ldo1vdd through to ldo10vdd respectively. the ldo input supply pins are typically connec ted to the sysvdd voltage node, or else can be connected to the output pin of one of the dc-dc buck c onverters. note that t he internal supply pins pvdd1 and pvdd2 should also be connected to sysvdd. ldo11 is a configurable ldo intended for ?alway s-on? functions external to the WM8310. the WM8310 contains a further two non-configurable ld os which support inter nal functions only. the connections to ldo regulator 1 are illustrated in figure 22. the equivalent circuit applies to ldo2 through to ldo10. figure 22 ldo regulator connections an input and output capacitor are recommended fo r each ldo regulator, as illustrated above. see section 30.5 for details of spec ific recommended external components.
pre-production WM8310 w pp, may 2012, rev 3.1 99 16 current sinks 16.1 general description the WM8310 provides two current sinks, isink1 and isink2. these are programmable constant- current sinks designed to drive strings of seria lly connected leds, including white leds used in display backlight applications. the WM8310 boost converter, dc-dc4, is designed as a power source for led strings. driving leds in this way is particularly power efficient because no series resistor is required. the boost converter can generate voltages higher than the battery, wall or usb supply, producing the necessary combined forward voltages of long led st rings. see section 15.15.3 for details of dc-dc4 operation. 16.2 current sink control the configuration of the current sinks is described in the following sections. 16.2.1 enabling the sink current in the on power state, the current sinks isink1 and isink2 can be enabled in software using the cs1_ena and cs2_ena register fiel ds as defined in table 48. when the current sinks are enabled, the drive current is controlled by the cs1_drive and cs2_drive bits. note that the current sinks permit current flow only when the applicable cs n _ena and cs n _drive bits are both set. the WM8310 boost converter, dc-dc4, is the reco mmended power source for the current sinks. the recommended switch-on sequence is as follows: ? enable current sink and current drive (cs n _ena = 1; cs n _drive = 1) ? enable boost converter (dc4_ena = 1) the status of the current sinks in the sleep power state are controlled by cs1_slpena and cs2_slpena, as described in table 48. the curr ent sinks may either be disabled in sleep or remain under control of the applicable cs n _ena register bit. if a current sink is disabled in sleep, then the applicable cs n _drive bit is automatically reset to 0 as part of the sleep transition sequence. note that the cs n _drive bit will remain reset at 0 following a wake transition; the current sink c an only be re-enabled by writing to the applicable cs n _drive register bit. if both current sinks are disabled in sleep, then dc4 can also be disabled in sleep, by setting dc4_slpena = 0, as described in section 15.4.2. if dc4 is not disabled, then it is important that cs n _ena also remains set in the sleep power state. the recommended switch-off sequence for dc-dc4 and the current sinks is as follows: ? disable current drive (cs n _drive = 0) ? disable boost converter (dc4_ena = 0) ? disable current sink (cs n _ena = 0) note that this switch-off sequence is important in order to avoid forward-biasing on-chip esd protection diodes.
WM8310 pre-production w pp, may 2012, rev 3.1 100 when the current sinks output drive is enabled or disabled using cs1_drive or cs2_drive, the current ramps up or down at a programmable rate . the ramp durations are programmed using the register bits defined in section 16.2.3. if the curr ent ramp is not required when switching off dc-dc4 and the current sinks, then the following switch-off sequence may be used: ? disable boost converter (dc4_ena = 0) ? disable current sink and current drive (cs n _ena = 0; cs n _drive = 0) when the current sinks are enabled, the status of each is indicated using the csn_sts bits. if the current sinks are unable to sink the demanded current ( eg. if the power source is too low or if the load is open circuit), then the respecti ve csn_sts bit will be set to 1. when the current sink circuit is correctly regulated, then the respecti ve csn_sts bits are set to 0. address bit label default description r16462 (404eh) current sink 1 15 cs1_ena 0 current sink 1 enable (isink1 pin) 0 = disabled 1 = enabled note - this bit is reset to 0 when the off power state is entered. 14 cs1_drive 0 current sink 1 output drive enable 0 = disabled 1 = enabled 13 cs1_sts 0 current sink 1 status 0 = normal 1 = sink current cannot be regulated 12 cs1_slpena 0 current sink 1 sleep enable 0 = disabled 1 = controlled by cs1_ena r16463 (404fh) current sink 2 15 cs2_ena 0 current sink 2 enable (isink2 pin) 0 = disabled 1 = enabled note - this bit is reset to 0 when the off power state is entered. 14 cs2_drive 0 current sink 2 output drive enable 0 = disabled 1 = enabled 13 cs2_sts 0 current sink 2 status 0 = normal 1 = sink current cannot be regulated 12 cs2_slpena 0 current sink 2 sleep enable 0 = disabled 1 = controlled by cs2_ena table 48 enabling isink1 and isink2 16.2.2 programming the sink current the sink currents for isink1 and isink2 can be independently programmed by writing to the cs1_isel and cs2_isel register bits. the current st eps are logarithmic to match the logarithmic light sensitivity characteristic of the human eye. the step size is 1.51db (i.e. the current doubles every four steps). note that the maximum programmable sink current is 27.6ma. the maximum current that can be supported by the dc-dc4 boost converter varies wi th the output voltage; the maximum isink current that can be supported by the boost converter will depend upon the forward voltage required by the current sink load(s).
pre-production WM8310 w pp, may 2012, rev 3.1 101 address bit label default description r16462 (404eh) current sink 1 5:0 cs1_isel 00 0000 isink1 current. current = 2.0a 2^(cs1_isel/4), where cs1_isel is an unsigned binary number. alternatively, cs1_isel = 13.29 x log(current/2.0a) 00_0000 = 2.0a 11_0111 = 27.6ma values greater than 11_0111 will result in the maximum current of approx 27.6ma. r16463 (404fh) current sink 2 5:0 cs2_isel 00 0000 isink2 current. current = 2.0a 2^(cs2_isel/4), where cs2_isel is an unsigned binary number. alternatively, cs2_isel = 13.29 x log(current/2.0a) 00_0000 = 2.0a 11_0111 = 27.6ma values greater than 11_0111 will result in the maximum current of approx 27.6ma. table 49 controlling the sink current for isink1 and isink2 16.2.3 on/off ramp timing when the current sinks output drive is enabled or disabled using cs1_drive or cs2_drive, the current ramps up or down at a programmable rate. this can be used in order to switch the leds on or off gradually. the ramp durations are programmed using the register bits defined in table 50. address bit label default description r16462 (404eh) current sink 1 11:10 cs1_off_ra mp 01 isink1 switch-off ramp 00 = instant (no ramp) 01 = 1 step every 4ms (220ms) 10 = 1 step every 8ms (440ms) 11 = 1 step every 16ms (880ms) the time quoted in brackets is valid for the maximum change in current drive setting. the actual time scales according to the extent of the change in current drive setting. 9:8 cs1_on_ram p 01 isink1 switch-on ramp 00 = instant (no ramp) 01 = 1 step every 4ms (220ms) 10 = 1 step every 8ms (440ms) 11 = 1 step every 16ms (880ms) the time quoted in brackets is valid for the maximum change in current drive setting. the actual time scales according to the extent of the change in current drive setting.
WM8310 pre-production w pp, may 2012, rev 3.1 102 address bit label default description r16463 (404fh) current sink 2 11:10 cs2_off_ra mp 01 isink2 switch-off ramp 00 = instant (no ramp) 01 = 1 step every 4ms (220ms) 10 = 1 step every 8ms (440ms) 11 = 1 step every 16ms (880ms) the time quoted in brackets is valid for the maximum change in current drive setting. the actual time scales according to the extent of the change in current drive setting. 9:8 cs2_on_ram p 01 isink2 switch-on ramp 00 = instant (no ramp) 01 = 1 step every 4ms (220ms) 10 = 1 step every 8ms (440ms) 11 = 1 step every 16ms (880ms) the time quoted in brackets is valid for the maximum change in current drive setting. the actual time scales according to the extent of the change in current drive setting. table 50 configuring on/off ramp timing for isink1 and isink2 16.3 current sink interrupts the current sinks are associated with two interrupt event flags, which indicate if the current sinks are unable to sink the demanded current (eg. if the power source is too low or if the load is open circuit). each of these secondary interrupts trigger s a primary current sink interrupt, cs_int (see section 23). this can be masked by setting t he mask bit(s) as described in table 51. address bit label description r16402 (4012h) interrupt status 2 7 cs2_eint current sink 2 interrupt (rising edge triggered) note: cleared when a ?1? is written. 6 cs1_eint current sink 1 interrupt (rising edge triggered) note: cleared when a ?1? is written. r16410 (401ah) interrupt status 2 mask 7 im_cs2_eint interrupt mask. 0 = do not mask interrupt. 1 = mask interrupt. default value is 1 (masked) 6 im_cs1_eint interrupt mask. 0 = do not mask interrupt. 1 = mask interrupt. default value is 1 (masked) table 51 current sink interrupts
pre-production WM8310 w pp, may 2012, rev 3.1 103 16.4 led driver connections the recommended connections for leds on isink1 and isink2 are illustrated in figure 23. WM8310 isink1 vdd isinkgnd note: equivalent circuit applies for isink2 figure 23 led connections to isink1 and isink2 the ground connection associated with these two cu rrent sinks is the isinkgnd pin. the dc-dc4 boost converter can be used to prov ide the vdd supply for isink1 or isink2. it is also possible to drive isink1 and isink2 simultaneously from the dc-dc4 boost converter. see section 15.4.2 for details of configuring dc-dc4 correctly according to whether it is supplying isink1 or isink2.
WM8310 pre-production w pp, may 2012, rev 3.1 104 17 power supply control 17.1 general description the WM8310 can take its power supply from a wall adaptor, a usb interface or from a single-cell lithium battery. the WM8310 autonomously chooses t he most appropriate power source available, and supports hot-swapping between sources (ie. the sy stem can remain in operation while different sources are connected and disconnected). comparators within the WM8310 identify which power supplies are available and select the power source in the following order of preference: ? wall adaptor (wallvdd) ? usb power rail (usbvdd) ? battery (battvdd) note that the wall supply is normally the first choice of supply, provided that it is within the operating limits quoted in section 6. the WM8310 can operate with any combination of these power supplies, or with just a single supply. when wallvdd or usbvdd is selected as the pow er source, this may be used to charge the battery, using the integrated battery charger circuit. the recommended connections between the WM8310 and the wall, usb and battery supplies are illustrated in figure 24. note that the external fet components may be omitted in some applications; as described later in this section. figure 24 WM8310 power supply connections sysvdd is primarily an output from the WM8310; th is output is the preferred supply, where the WM8310 has arbitrated between the wall, battery and usb connections. this output is suitable for supplying power to the other blocks of the WM8310, including the dc-dc converters and ldo regulators. sysvdd is also an input under some c onditions, such as battery charging from the wall supply. the voltage at the sysvdd load connecti on point is sensed using the sysvmon pin. all loads connected to the WM8310 should be connected to the sysvdd pin. the inputs to the dc- dc converters and ldos are typically connected to the sysvdd pin. the inputs to the ldos may, alternatively, be connected to the outputs of the dc-dcs if desired.
pre-production WM8310 w pp, may 2012, rev 3.1 105 note that connecting the battvdd pin directly to a load is not recommended; this may lead to incorrect behaviour of the battery charger. a filter capacitor between battvdd and gnd is recommended to ensure best performance of the battery charger; for specific recommendations, refer to the WM8310 evaluation board users manual. the wall adaptor supply connects to sysvdd via a fe t switch as illustrated in figure 24. the fet switch is necessary in order to provide is olation between the wall supply and the battery/usb supplies. the wall adapter voltage is sensed dire ctly on the wallvdd pin; this allows the WM8310 to determine the preferred supply, incl uding when the wall fet is switched off. the gate connection to the wall fet is driven by the wallfetena pin. the drive strength of this pin can be selected using the wall_fet_ena_drv_str register bit as described in section 17.3. note that, when the wall adapter is the preferred power supply, the battery will be used if necessary to supplement the current provided at sysvdd. if the wall adapter power source is not used, then the associated fet may be omitted, as illustrated in figure 24. the main battery connects directly to the battvdd pin. the voltage at the battery is sensed using the battvmon pin. it is highly recommended that an external fe t is connected between battvdd and sysvdd as illustrated in figure 24. under battery-powered operation, this fet controls the current flow from the battery to sysvdd. by using this external pat h, the power losses under heavy load conditions are reduced, and power efficiency is incr eased. when this fet is not present, all the system current flows internally from battvdd to sysvdd, which can l ead to unnecessary thermal losses. the external battery fet should always be used fo r average loads in excess of 1a. the gate connection to the battery fet is driven by the battfetena pin. t he functionality of this pin is enabled by setting the batt_fet_ena regi ster bit, as described in section 17.2. if the average load drawn from the battery is less than 1a, then the associated fet may be omitted, as illustrated in figure 24. note that the external fet is open during battery charging. the usb interface connects directly to the usbvdd pin. the WM8310 can use this pin as an input to power the device and/or to charge a battery connec ted to the battvdd pin. the voltage at the usb supply is sensed usi ng the usbvmon pin. note that, when usb is the preferred power supply, the battery will be used if necessary to supplement the current drawn from the usbvdd pin. a backup power source can be supported using a coin cell, super/gold capacitor, or else a standard capacitor, connected to the ldo12v out pin. when no other supply is available, the backup source provides power to maintain the rtc memory whilst in the backup power state. at other times, the ldo12vout pin provides a cons tant-voltage output to maintain the backup power source. see section 17.6 for more details of backup power. the status of the wall and usb power supplies is indicated in the system status register, as described in table 52. when pwr_wall or pwr_usb is set, this indicates that the corresponding power source is available for powering the WM8310. if the status of either these power supplies changes, indicating a connecti on, disconnection, or a voltage that is outside the required limits, the po wer path source interrupt, ppm_pwr_src_eint, is set (see section 17.5). note that this interrupt does not indicate the availability of the battery power source. the pwr_src_batt bit indicates when the battery is supplying current to the WM8310. this includes when the battery is supplementing the wall or usb power supply sources.
WM8310 pre-production w pp, may 2012, rev 3.1 106 address bit label default description r16397 (400dh) system status 10 pwr_src_batt 0 battery power source status 0 = battery is not supplying current 1 = battery is supplying current 9 pwr_wall 0 wall adaptor status 0 = wall adaptor voltage not present 1 = wall adaptor voltage is present 8 pwr_usb 0 usb status 0 = usb voltage not present 1 = usb voltage is present table 52 power source status registers 17.2 battery powered operation the WM8310 selects battery power via battvdd when the battery voltage is higher than the wallvdd and usbvdd supply voltages. in practical usage, this means the battery is used when the wall and usb supplies are both disconnected. the battery will be used to supplement the u sb or wall adaptor supplies when required. if the wallvdd or usbvdd supply bec omes available during battery operation, then the selected power source is adjusted accordingly. when an external fet is prov ided between battvdd and sysvdd, as described in section 17.1, the battfetena pin func tionality must be enabled by setting batt_fet_ena as described in table 53. address bit label default description r16390 (4006h) reset control 12 batt_fet_ena 0 enables the fet gate functionality on the battfetena pin. (note this pin is active low.) 0 = disabled 1 = enabled note - this bit is reset to 0 when the off power state is entered. table 53 configuring the battery power operation 17.3 wall adaptor powered operation the WM8310 selects wall adaptor power whenever this supply is within the normal operating limits of 4.3v to 5.5v and wallvdd is higher than battv dd. the wall adaptor power source is also selected below 4.3v if usbvdd is less than 4.3v and wallvdd is higher than battvdd. note that usbvdd supply is not used when wallvdd is within its normal operating limits, even if the usbvdd supply is higher than the wallvdd supply. when the wallvdd supply is selected and a battery is connected, then battery charging is possible in the on or sleep power states; see section 17.7. the drive strength of the wall fet gate connection, wallfetena , can be sele cted using the wall_fet_ena_drv_str register bit as described in table 54. address bit label default description r16390 (4006h) reset control 13 wall_fet_ena_d rv_str 0 sets the drive strength of the wallfetena pin. (note this pin is active low.) 0 = weak drive (500kohm) 1 = strong drive (50kohm) table 54 configuring the wall adaptor power operation
pre-production WM8310 w pp, may 2012, rev 3.1 107 17.4 usb powered operation the WM8310 selects usb power via the usbvdd pin when this supply is within the normal usb operating limits of 4.3v to 5.5v, and wallvdd is less than 4.3v and usbvdd is the highest supply source available. usb power is also select ed below 4.3v if wallvdd is less than 3.4v and usbvdd is the highest supply available. the maximum current drawn from the usb supply is determined by the usb_ilim register field. currents ranging from 0ma to 1800ma may be selected. see also section 7 for the limits of the usb current switch. if the system current demand is great er than the limit set by usb_ilim, then this is indicated via the usb_curr_sts bit and by setting the ppm_usb_curr_eint interrupt (see section 17.5). the usb power source will be supplemented by battery power, when available, in order to maintain the usb current within the applicable limit. if there is no battery connected, or there is insufficient capacity to support the system demands, then the s upply rails may drop as the WM8310 attempts to meet the usb current limit. if a suitable wallvdd supply becomes available during usb operation, then this will be selected as the preferred power source. when the usbvdd supply is selected and a battery is connected, then battery charging is possible in the on or sleep power states, provided that su fficient current capacity is available. see section 17.7 for details of the battery charger. note that, when the usbvdd supply is selected by the WM8310, and an ?on? state transition is requested, the usb current limit must be set to 100m a or higher. if a lower current limit is selected, then the ?on? state transition event may fail. this requirement is also applicable when a battery is available to provide supplementary power. there is no requirement to set usb_ilim for start-up when the wallvdd supply is selected. the user-configurable otp memory c ontains the usb_ilim register field. this allows users to program their chosen usb current limit on start- up (note that the current limit can still be updated during normal operation.) if the WM8310 is powered up with usbvdd as the selected power source, and the applicable usb current limit is 100ma, t hen the start-up behaviour is determined by the usb100ma_startup field, as defined in table 55. when starting up in 100ma usb mode, the normal or soft-start process can be selected. the soft- start option controls the dc-dc conv erters and ldo regulators in order to reduce the start-up current demand. in 100ma usb soft-start operation, the dc- dc converters are initially enabled in ldo mode in order that the in-rush current does not exceed the usb limit. the ldo regulators are also current- limited during the soft start-up. care is required when using the 100ma soft-start; if the ldos or dc-dcs present an excessive load, then the WM8310 may be unable to power up; it must be ensured that the connected load is compatible with the 100ma current limit. in particu lar, it is important that the loads on the dc-dc converters do not exceed the capacity of thei r ldo operating modes. (see section 7.1 for the maximum current in ldo mode.) it is also possible to delay the usb start-up if the battery voltage is less than a selectable threshold; in these cases, the WM8310 enables the battery tri ckle charge mode (provided that chg_ena = 1), and delays the start-up request until the battery voltage threshold has been met. see also section 27.1 for specific external component requirements relating to the usb100ma_startup register setting.
WM8310 pre-production w pp, may 2012, rev 3.1 108 address bit label default description r16387 (4003h) power state 5:4 usb100ma_start up [1:0 00 sets the device behaviour when starting up under usb power, when usb_ilim = 010 (100ma) 00 = normal 01 = soft-start 10 = only start if battvdd > 3.1v 11 = only start if battvdd > 3.4v in the 1x modes, if the battery voltage is less than the selected threshold, then the device will enable trickle charge mode instead of executing the start-up request. the start-up request is delayed until the battery voltage threshold has been met. note that trickle charge is only possible when chg_ena=1. 3 usb_curr_sts 0 indicates if the usb current limit has been reached 0 = normal 1 = usb current limit 2:0 usb_ilim 010 sets the usb current limit 000 = 0ma (usb switch is open) 001 = 2.5ma 010 = 100ma 011 = 500ma 100 = 900ma 101 = 1500ma 110 = 1800ma 111 = 550ma note that, when starting up the WM8310 with the usbvdd supply selected, the usb_ilim register must be set to 100ma or higher. table 55 configuring the usb power operation 17.5 power path management interrupts the power path management circuit is asso ciated with three interrupt event flags. the ppm_syslo_eint interrupt bit is set when the in ternal signal syslo is asserted. this indicates a sysvdd undervoltage condition, described in section 24.4. the ppm_pwr_src_eint interrupt bit is set whenev er the status of the wall or usb supplies changes, indicating a connecti on, disconnection, or a voltage. see section 17.1. the ppm_usb_curr_eint interrupt bit is set w henever the permitted usb current limit has been reached. see section 17.4. each of these secondary interrupts triggers a pr imary power path management interrupt, ppm_int (see section 23). this can be masked by setting the mask bit(s) as described in table 56.
pre-production WM8310 w pp, may 2012, rev 3.1 109 address bit label description r16401 (4011h) interrupt status 1 15 ppm_syslo_eint power path syslo interrupt (rising edge triggered) note: cleared when a ?1? is written. 14 ppm_pwr_src_eint power path source interrupt (rising edge triggered) note: cleared when a ?1? is written. 13 ppm_usb_curr_eint power path usb current interrupt (rising edge triggered) note: cleared when a ?1? is written. r16409 (4019h) interrupt status 1 mask 15 im_ppm_syslo_eint interrupt mask. 0 = do not mask interrupt. 1 = mask interrupt. default value is 1 (masked) 14 im_ppm_pwr_src_eint interrupt mask. 0 = do not mask interrupt. 1 = mask interrupt. default value is 1 (masked) 13 im_ppm_usb_curr_ein t interrupt mask. 0 = do not mask interrupt. 1 = mask interrupt. default value is 1 (masked) table 56 power path management interrupts 17.6 backup power as an option, a backup power source can be provi ded for the WM8310. this is provided using a coin cell, super/gold capacitor, or else a standard capacitor, connected to the ldo12vout pin. note that a 22k ? series resistor should also be c onnected to the backup power source. the ldo12vout pin provides a constant-voltage output for char ging the backup power source whenever the sysvdd power domain is available. the purpose of the backup is to power the always-on functions such as the crystal oscillator, rtc and alarm control registers. the backup power also maintains a ?software scratch? memory area in the register map - see section 12.6. maintaining these f unctions at all times provides system continuity even when the main battery is removed and no other power supply is available. the backup duration will vary depending upon the backup pow er source characteristics. a typical coin cell can provide power to the WM8310 in backup mode for a month or more whilst also maintainingthe rtc and the ?software scratch? register. if a standard capacitor is used as the backup power source, then it is particularly important to minimise the device power consumption in the backup state. a 22 ? f capacitor will maintain the device settings for up to 5 minutes in ?unclocked? mode, where power consumption is minimised by stopping the rtc in the backup state. the rt c is unclocked in the backup state if the xtal_bkupena register field is set to 0, as described in section 20.5. 17.7 battery charger 17.7.1 general description the WM8310 incorporates a battery charger whic h is designed for charging single-cell lithium batteries. the battery charger can operate from eit her the wall or usb power sources. the battery charger implements constant-current (cc) and c onstant-voltage (cv) charge methods, and can run automatically without any intervention required by the host processor.
WM8310 pre-production w pp, may 2012, rev 3.1 110 the battery charger voltage and current are progra mmable. trickle charging and fast charging modes are supported. in both modes, the sysvdd voltage is monitored to ensure the power supply capacity or usb current limit is not exceeded. if the sysvdd voltage drops to 3.9v, (eg. if the usb current limit has been reached), then the battery charge curr ent is automatically reduced to try and prevent further voltage drop at sysvdd. under high operating load conditions , the battery may be required to supplement the usb or wall adaptor power sources. note that this capabilit y is supported even when ba ttery charging is enabled; in this case, the battery provides power to the system when required, and the charger resumes when sufficient current capacity is available. typical connections for the WM8310 battery charger are illustrated in figure 25. WM8310 ntc ntcmon battvdd gnd led1 charge status indicator led charge current battery temperature measurement primary power source secondary power source - used when primary is unavailable usbvdd sysvdd usb host 100k ntcbias battery monitor source single-cell lithium battery main battery connection system status led output wallvdd wallfetena wall adaptor supply sysvdd figure 25 typical connections for WM8310 battery charger the main battery terminal is connected to ba ttvdd. the WM8310 also incorporates a battery temperature monitoring circuit, which monitors the ntc thermistor that is typically incorporated within a rechargeable battery pack. the ntcmon pin allows the charger to detect a hot or cold battery condition that may be outside the battery?s usable operating conditions. battery removal is also detected using the ntcmon pin. the bias resistor connected between ntcbias and nt cmon should be a 1% tolerance resistor with a nominal value equal to the value of the battery?s ntc thermistor at 25 ? c. the temperature monitoring circui t can be disabled by shorting ntcm on to ldo12vout. this is only recommended if there is no ntc thermistor in corporated in the battery pack or if battery temperature monitoring is provided by other me thods. note that the short between ntcmon and ldo12vout is only sensed during start-up; the temperature monitoring circuit cannot be enabled / disabled dynamically in the on or sleep power states. see section 17.7.7 for more details of t he battery temperature monitoring function. a typical battery charge cycle is illustrated in fi gure 26. this shows both the trickle charge and fast charge processes. the trickle charge mode is a constant current mode. the small charge current in this mode is suitable for pre-conditioning a deeply dischar ged battery, or when only limited power is available for battery charging. when the charger is enabl ed and the conditions for fast c harging are not met, then trickle charging is selected. (note that fast charging is not permitted if the battery voltage is below the defective battery threshold volt age.) trickle charging is disabled when the charger enters the fast charging stage, or when the charge current drops to a programmable ?end of charge? threshold level at the end of the constant voltage charge phase.
pre-production WM8310 w pp, may 2012, rev 3.1 111 the fast charge mode is also a constant current mode, but higher charge currents are possible in this mode. in the fast charge phase, the WM8310 drives a programmable constant current into the battery through the battvdd pin. during this phase, the ba ttery voltage rises until the battery reaches the target voltage. when the battery reaches the target voltage (through trickle charge and/or fast charge), the charger enters the constant voltage charge phase, in wh ich the WM8310 regulates battvdd to the target voltage. during this phase of the charge process, the charge current decreas es over time as the battery approaches its fully charged state. battery c harging is terminated when the current falls to a programmable ?end of charge? threshold level at the end of the constant voltage charge phase. note that, at any time during trickle charging or fast charging, the battery may be required to supplement the usb or wall adaptor power source. in this case, the battery voltage may drop while it is providing power to the system. the charger re sumes operation automatically as soon as sufficient current capacity is available from the main power source. after the battery has been fully charged and the char ge process has terminated, battery charging will automatically re-start if the battery voltage falls below the charger re-start threshold. figure 26 a typical charge cycle 17.7.2 battery charger enable the battery charger may be enabled when the WM8310 is in the on or sleep power states. note that battery charging is only possible when the se lected power source is within normal operating limits. see section 17.7.8 for further details of battery charging in the sleep power state. the battery charger is enabled when the chg_ena regist er bit is set to 1. when enabled, it checks if the conditions for charging are fulf illed and it controls the charging pr ocesses accordingly. the status of the battery charger can be read from the chg_active register bit. the target voltage for the battery is set by the chg_ vsel field, as defined in table 57. it is important that this field is correctly set according to the type of battery that is connected. incorrect setting of this register may lead to a safety hazard condition. the trickle charge current is selected using the chg _trkl_ilim field. this is the maximum trickle charge current - the actual charge current will be r educed if the battery is fully charged, or if the system supply, sysvdd, drops as described in section 17.7.1. when the battery reaches the target voltage, the c harger enters the constant voltage charge phase, in which the WM8310 regulates battvdd to the target voltage. when the charger is in the constant voltage charge phase, then the chg_topoff bit w ill be set to indicate that the charge is approaching completion. the WM8310 incorporates thermal sensors to detect excessive temperatures within the device and to provide self-protection (see section 26). by default, the battery charger will be disabled if the thermal warning condition occurs, and will be re-enabled after the condition has cleared. this response can be disabled by setting chg_chip_temp_mon = 0, allowing the battery charge to continue. the thermal warning threshold is the lower of the two device temperature thresholds; the thermal shutdown threshold is the higher threshold. no te that the thermal shutdown condition cannot be ignored; this event causes a system rese t and a termination of battery charging.
WM8310 pre-production w pp, may 2012, rev 3.1 112 if the WM8310 is commanded to the off state for any reason, then battery charging will be terminated. the chg_off_mask bit can be used to prevent certain off transitions whilst the battery charger is active. setting the chg_off_m ask bit causes a ?softwar e off request?, ?on pin request? or gpio off request to be ignored whilst the charger is active. see section 11.3 for a full list of off transition events. the register control fields for tr ickle charging are described in table 57. see section 17.7.4 for details of battery charge termination. note that the battery charger control registers are locked by the WM8310 user key. these registers can only be changed by writing the appropriate code to the security register, as described in section 12.4. address bit label default description r16456 (4048h) charger control 1 15 chg_ena 0 battery charger enable 0 = disable 1 = enable protected by user key 0 chg_chip_temp_ mon 1 battery charger thermal warning select 0 = thermal warning is ignored 1 = thermal warning pauses battery charger protected by user key r16457 (4049h) charger control 2 14 chg_off_mask 0 battery charger off mask select 0 = off requests not masked 1 = off requests masked during charging protected by user key 7:6 chg_trkl_ilim [1:0] 00 battery trickle charge current limit 00 = 50ma 01 = 100ma 10 = 150ma 11 = 200ma protected by user key 5:4 chg_vsel [1:0] 00 battery charger target voltage 00 = 4.05v 01 = 4.10v 10 = 4.15v 11 = 4.20v note that incorrect setting of this register may lead to a safety hazard condition. protected by user key r16458 (404ah) charger status 9 chg_topoff 0 battery charger constant-voltage charge mode status 0 = constant-voltage mode not active 1 = constant-voltage mode is active 8 chg_active 0 battery charger status 0 = not charging 1 = charging table 57 battery charger control the battery charger is associated with a number of interrupt flags. whenever the battery charger state changes, the chg_mode_eint interrupt is se t (see section 17.7.8). this interrupt is set whenever charging starts, charging stops, fast charge is selected, fast charge is de-selected, an overtemperature condition occurs, or if the char ger detects a battery failure. the chg_start_eint interrupt is also set whenever battery charging commences, including after pause due to usb limit or over-temperature condition.
pre-production WM8310 w pp, may 2012, rev 3.1 113 17.7.3 fast charging fast charging provides a faster way to charge the battery than is possible with trickle charge. see section 17.7.1 for a description of fast charging. fast charging mode is only possible under certain conditions. it is only possible when the selected power source is wall or when the usb current limit is set to 500ma or more. it is also required that the battery voltage is above the fast charge voltage thre shold; this ensures that fast charging is not applied to a heavily discharged battery. fast charging is enabled by setting the chg_fast regi ster bit, provided that the conditions for fast charging are satisfied. the fast charge current limit is selected using the chg_fast_ilim field. the battery charge current is automatically contro lled, up to a maximum set by chg_fast_ilim. the current is automatically limited when required if the ba ttery is fully charged, or if the system supply, sysvdd, drops as described in section 17.7.1. the fast charge mode comprises two phases, as descr ibed in section 17.7.1. when the charger is in the constant voltage charge phase, the chg_topoff bi t will be set to indicate that the charge is approaching completion. when the battery reaches the target voltage, the c harger enters the constant voltage charge phase, in which the WM8310 regulates battvdd to the target voltage. when the charger is in the constant voltage charge phase, then the chg_topoff bit will be se t (see section 17.7.2) to indicate that the charge is approaching completion. the register control fields for fa st charging are described in table 58. note that the battery charger control registers are locked by the WM8310 user key. these registers can only be changed by writing the appropriate code to the security register, as described in section 12.4. address bit label default description r16456 (4048h) charger control 1 15 chg_fast 0 battery fast charge enable 0 = disable 1 = enable protected by user key r16457 (4049h) charger control 2 3:0 chg_fast_ilim [3:0] 0010 battery fast charge current limit 0000 = 0ma 0001 = 50ma 0010 = 100ma 0011 = 150ma 0100 = 200ma 0101 = 250ma 0110 = 300ma 0111 = 350ma 1000 = 400ma 1001 = 450ma 1010 = 500ma 1011 = 600ma 1100 = 700ma 1101 = 800ma 1110 = 900ma 1111 = 1000ma protected by user key table 58 fast charge control
WM8310 pre-production w pp, may 2012, rev 3.1 114 17.7.4 charger timeout and termination fast charging and trickle charging is term inated under any of the following conditions: ? charge current falls below the ?end of charge? threshold ? charger timeout ? battery fault or overvoltage condition (see section 17.7.6) ? chip overtemperature condition (see section 17.7.2) ? transition to the off power state the end of charge current threshold can be set usi ng the chg_iterm register field, as defined in table 59. charging is terminated when the charge current is below the chg_iterm threshold, provided also that the battery voltage has reached the target voltage chg_vsel at the end of the constant voltage charge phase. if the battery charger current is reduced or paus ed due to a drop in sysvdd voltage (as described in section 17.7.1), then the end of charge current threshold does not cause battery charging to be terminated, as the charge current is not indicati ve of the battery charge status in this case. the battery charger has a programmable safety timer to control the battery charge duration. the timer is started when either fast charging or trickl e charging commences, incl uding charging that is triggered as a result of the battery voltage dropping to the charger re-start thre shold. the timer is re- started if the charging mode is changed (eg. bet ween fast charge and trickle charge modes). the timeout period may be set by writing to the chg_time r egister field; this allows charge times of up to 510mins (8.5 hours) to be selected. when the timeout period completes, the battery charge cycle is terminated. in this event, the charger will not re-start until the charger has been dis abled (chg_ena = 0) and then re-enabled (chg_ena = 1). note that the charger re-start threshold is ignored in this case, and the charger will not re-start automatically. the elapsed battery charge time can be read from t he chg_time_elapsed register field. this field is reset whenever the charger timer is started (ie. by starting charging, st opping charging, or changing charging modes). if charging is paused due to a battery temperature or chip temperature condition, then the charge timer is paused until charging resumes. battery charging is terminated if removal of the battery is detected via t he ntc monitor connections (see section 17.7.2). the register control fields for battery charger te rmination are described in table 59. note that the battery charger control registers are locked by the WM8310 user key. these registers can only be changed by writing the appropriate code to the secu rity register, as described in section 12.4. address bit label default description r16456 (4048h) charger control 1 12:10 chg_iterm [2:0] 000 battery end of charge current threshold 000 = 20ma 001 = 30ma 010 = 40ma 011 = 50ma 100 = 60ma 101 = 70ma 110 = 80ma 111 = 90ma protected by user key
pre-production WM8310 w pp, may 2012, rev 3.1 115 address bit label default description r16457 (4049h) charger control 2 11:8 chg_time [3:0] 0110 battery charger timeout 0000 = 60min 0001 = 90min 0010 = 120min 0011 = 150min 0100 = 180min 0101 = 210min 0110 = 240min 0111 = 270min 1000 = 300min 1001 = 330min 1010 = 360min 1011 = 390min 1100 = 420min 1101 = 450min 1110 = 480min 1111 = 510min protected by user key r16458 (404ah) charger status 7:0 chg_time_el apsed [7:0] 00h battery charger elapsed time 00h = 0min 01h = 2min 02h = 4min 03h = 6min ... ffh = 510min table 59 battery charger termination the battery charger is associated with a number of interrupt flags, as described in section 17.7.8. if battery charging is terminated due to the end of charge current threshold being reached, then the chg_end_eint interrupt is set. if battery charging is terminated due to the charge timeout, then the charger will set the chg_to_eint interrupt. 17.7.5 battery charge current monitoring the battery charge current can be monitored exter nally or internally. when the chg_imon_ena bit is set, then the WM8310 sources an output current at auxadcin1 which is proportional to the battery charger current. when a resistor is connected between auxadcin1 and gnd, then the charge monitor current is converted to a voltage which can be measured by the auxiliary adc. the recommended value of the resistor is 10k ? . larger resistors may also be used in order to improve the measurement resolution, but the voltage at auxadcin1 must not exceed 2.5v. note that the chg_imon_ena register is locked by the WM8310 user key. this register can only be changed by writing the appropriate code to the secu rity register, as described in section 12.4. address bit label default description r16456 (4048h) charger control 1 2 chg_imon_e na 0 enable battery charge current monitor at auxadcin1. 0 = disabled 1 = enabled (note - a resistor is required between auxadcin1 and gnd in order to measure the charge current using the auxadc. the recommended resistor value is 10k.) protected by user key table 60 battery charge current monitoring
WM8310 pre-production w pp, may 2012, rev 3.1 116 the auxadcin1 monitor output current is equal to the battery charge current divided by 12500. the battery charge current can be determined by meas uring the voltage at the auxadcin1 pin, as described in the following equations. monitor current i m = = charge current i c 12500 v auxadcin1 r charge current i c = v auxadcin1 x 12500 10000 (assuming 10k resistor, r) for example, a measurement of 0.72v at auxadcin1 would indicate that the battery charge current is 900ma. note that the integrated auxiliary adc can be used to perform this measurement if required. in this case, the digitised auxadc measurement (aux_dat a) represents the battery charge current in accordance with the following equation. see section 18 for further details of the auxiliary adc. 17.7.6 battery fault / overvoltage conditions the battery is monitored to detect an overvoltage or failure condition. these features are incorporated to prevent malfunction of the battery charger or of the WM8310 system. the batt_ov_sts bit indicates if an overvo ltage condition has been detected. the overvoltage threshold is defined in section 7.7. if a battery overvoltage condition is det ected, then charging is terminated and the chg_ov_eint interrupt flag is set (see section 17.7.8). the battery charger also detects if the battery is f aulty. this is detected if the battery voltage does not reach the fast charge threshold voltage within the defective battery timeout period (see section 7.7), or within a quarter of the charging time chg_time (whichever is the longer time). the battery failure condition is cleared if the battery voltage rises above the defective battery threshold, or if any of the WM8310 power sour ces (including the battery) is removed and re- connected. when the failure condition is cleared, the charger then revert s back to its initial state, and may re-start if the conditions for charging are fulfilled. if the battery failure condition is detected in fast charge mode, then the charger reverts to trickle charging mode. if the fault persists, then trickle charging stops as described above. if battery failure condition is detected, then c harging is terminated and the chg_batt_fail_eint interrupt is set (see section 17.7.8). the battery overvoltage bit is defined in table 61. address bit label default description r16458 (404ah) charger status 15 batt_ov_sts 0 battery overvoltage status 0 = normal 1 = battery overvoltage table 61 battery overvoltage status
pre-production WM8310 w pp, may 2012, rev 3.1 117 17.7.7 battery temperature monitoring as described in section 17.7.1, the WM8310 is des igned to monitor battery temperature using a standard ntc thermistor component which is typically incorporated within the battery pack. this allows the battery charger to detect a hot or cold battery condition that may be outside the battery?s usable operating conditions. (note that the temperature monitori ng circuit also detects if the ntc circuit is not connected, in order to mask any erroneous fault indications.) the batt_hot_sts and batt_cold_sts register bits indicate if a hot battery or cold battery temperature condition has been detected. if a battery temperature fault condition is detected, then charging is paused temporarily and the chg_ batt_hot_eint or chg_batt_cold_eint interrupt is set (see section 17.7.8). under typical circuit configurat ions, the hot and cold temperatur e conditions are designed to be +40 ? c and 0 ? c respectively. these temperatures can be adj usted by the use of different resistor components, as described in the applicat ions information in section 30.6. battery removal is also detected using the ntc circui t. this is used to terminate battery charging if a battery is removed during charging. the temperature monitoring circui t can be disabled by shorting ntcm on to ldo12vout. this is only recommended if there is no ntc thermistor in corporated in the battery pack or if battery temperature monitoring is provided by other me thods. note that the short between ntcmon and ldo12vout is only sensed during start-up; the temperature monitoring circuit cannot be enabled / disabled dynamically in the on or sleep power states. the battery temperature status bits are described in table 62. address bit label default description r16458 (404ah) charger status 11 batt_hot_st s 0 battery hot status 0 = normal 1 = battery hot 10 batt_cold_ sts 0 battery cold status 0 = normal 1 = battery cold table 62 battery temperature status battery temperature monitoring is configured as illust rated in figure 27. the principle of operation is that a temperature change in the battery pack caus es a change in resistance of the ntc thermistor, which results in a voltage change at the ntcmon pin. WM8310 ntc ntcmon battvdd gnd battery temperature measurement 100k ntcbias battery monitor source single-cell lithium battery main battery connection ntc bias resistor r bias (100k) ntc thermistor r ntc (100k at 25 c) v ntcmon = x v ntcbias r ntc 100k + r ntc figure 27 battery temperature monitoring
WM8310 pre-production w pp, may 2012, rev 3.1 118 for information on how to set the hot and cold temper ature limits, see the applications information in section 30.6. 17.7.8 battery charger interrupts the battery charger is associated with a number of interrupt event flags, described in table 63. each of these secondary interrupts triggers a primary ba ttery charger interrupt, chg_int (see section 23). this can be masked by setting the mask bit(s) as described in table 63. if any battery charger interrupt event occurs while in the sleep power state, then a wake transition request is generated. note that this behaviour is not affected by any of the interrupt mask bits. see section 11.3 for a description of the WM8310 power state transitions. if any of the battery charger interrupts is asserted when a sleep transition is requested, then the transition will be unsuccessful and the WM8310 will remain in the on power state. if battery charging is commenced in the sleep power state, the WM8310 will transition to the on power state, as a result of the chg_start_eint interrupt. battery charging in the sleep power state is only possible by clearing the chg_start _eint interrupt before commanding the transition into the sleep power state. address bit label description r16402 (4012h) interrupt status 2 15 chg_batt_hot_eint battery hot interrupt (rising edge triggered) note: cleared when a ?1? is written. 14 chg_batt_cold_eint battery cold interrupt (rising edge triggered) note: cleared when a ?1? is written. 13 chg_batt_fail_eint battery fail interrupt (rising edge triggered) note: cleared when a ?1? is written. 12 chg_ov_eint battery overvoltage interrupt (rising edge triggered) note: cleared when a ?1? is written. 11 chg_end_eint battery charge end interrupt (end of charge current threshold reached) (rising edge triggered) note: cleared when a ?1? is written. 10 chg_to_eint battery charge timeout interrupt (charger timer has expired) (rising edge triggered) note: cleared when a ?1? is written. 9 chg_mode_eint battery charge mode interrupt (charger mode has changed) (rising edge triggered) note: cleared when a ?1? is written. 8 chg_start_eint battery charge start interrupt (charging has started) (rising edge triggered) note: cleared when a ?1? is written. r16410 (401ah) interrupt status 2 mask 15 im_chg_batt_hot_eint interrupt mask. 0 = do not mask interrupt. 1 = mask interrupt. default value is 1 (masked) 14 im_chg_batt_cold_ein t interrupt mask. 0 = do not mask interrupt. 1 = mask interrupt. default value is 1 (masked) 13 im_chg_batt_fail_eint interrupt mask. 0 = do not mask interrupt.
pre-production WM8310 w pp, may 2012, rev 3.1 119 address bit label description 1 = mask interrupt. default value is 1 (masked) 12 im_chg_ov_eint interrupt mask. 0 = do not mask interrupt. 1 = mask interrupt. default value is 1 (masked) 11 im_chg_end_eint interrupt mask. 0 = do not mask interrupt. 1 = mask interrupt. default value is 1 (masked) 10 im_chg_to_eint interrupt mask. 0 = do not mask interrupt. 1 = mask interrupt. default value is 1 (masked) 9 im_chg_mode_eint interrupt mask. 0 = do not mask interrupt. 1 = mask interrupt. default value is 1 (masked) 8 im_chg_start_eint interrupt mask. 0 = do not mask interrupt. 1 = mask interrupt. default value is 1 (masked) table 63 battery charger interrupts 17.7.9 battery charger status the status of the battery charger can be read fr om various registers and interrupts noted in the above sections. the battery charger status can also be read from the chg_state register field, as defined in table 64. note that the led status outputs can also be c onfigured to indicate the battery charger - see section 22. address bit label default description r16458 (404ah) charger status 14:12 chg_state [2:0] 000 battery charger state 000 = off 001 = trickle charge 010 = fast charge 011 = trickle charge overtemperature 100 = fast charge overtemperature 101 = defective 110 = reserved 111 = reserved table 64 battery charger state
WM8310 pre-production w pp, may 2012, rev 3.1 120 18 auxiliary adc 18.1 general description the WM8310 incorporates a 12-bit auxiliary adc (a uxadc). this can be used to perform a number of system measurements (including supply voltages and battery temperature) and can also be used to measure analogue voltages from ex ternal sources and sensors. external inputs to the auxadc should be c onnected to the pins auxadcin1, auxadcin2, auxadcin3 and auxadcin4. the maximum voltage that can be measured is determined by the power domain associated with each (see section 3). in the case of auxadcin 1-3, the maximum voltage is sysvdd; in the case of auxadcin4, the maximum voltage is dbvdd. note that sysvdd varies according to the voltage of the prefe rred power source (wallvdd, usbvdd or battvdd). the auxadc can also measure the voltage on wallvdd, usbvdd and battvdd. internal resistor dividers enable voltages higher than sysv dd to be measured by the auxadc - voltages up to 6v can be measured on these pins. 18.2 auxadc control the auxadc is enabled by setting the aux_ena regi ster bit. by default, the auxadc is not enabled in the sleep state, but this can be selected using the aux_slpena field. the auxadc measurements can be initiated manually or automatically. for automatic operation, the aux_rate register is set according to the r equired conversion rate, and conversions are enabled by setting the aux_cvt_ena bit. for manual operation, the aux_rate register is set to 00h, and each manual conversion is initiated by setting the aux_cvt_ena bit. in manual mode, the aux_cvt_ena bit is reset by the WM8310 after each c onversion. (note that the conversion result is not available for readback until the auxadc interrupt is asserted as described in section 18.5.) the auxadc has 10 available input sources. ea ch of these inputs is enabled by setting the respective bit in the auxadc source register (r16431). for each auxadc measurement ev ent (in manual or automatic modes), the WM8310 selects the next enabled input source. any number of inputs may be selected simultaneously; the auxadc will measure each one in turn. note that only a single auxadc measurement is made on any manual or automatic trigger. for example, if the aux1, batt and usb voltages are enabled for auxadc measurement, then aux1 would be measured in the first instance, and batt then usb would be measured on the next manual or automatic auxadc triggers. in this ca se, a total of three manual or automatic auxadc triggers would be required to measure all of the selected inputs. the control fields associated with initiati ng auxadc measurements are defined in table 65. address bit label default description r16430 (402eh) auxadc control 15 aux_ena 0 auxadc enable 0 = disabled 1 = enabled note - this bit is reset to 0 when the off power state is entered. 14 aux_cvt_ena 0 auxadc conversion enable 0 = disabled 1 = enabled in automatic mode, conversions are enabled by setting this bit. in manual mode (aux_rate = 0), setting this bit will initiate a conversion; the bit is reset automatically after each conversion. 12 aux_slpena 0 auxadc sleep enable 0 = disabled 1 = controlled by aux_ena
pre-production WM8310 w pp, may 2012, rev 3.1 121 address bit label default description 5:0 aux_rate [5:0] 00_0000 auxadc conversion rate 0 = manual 1 = 2 samples/s 2 = 4 samples/s 3 = 6 samples/s ? 31 = 62 samples/s 32 = reserved 33 = 16 samples/s 34 = 32 samples/s 35 = 48 samples/s ? 63 = 496 samples/s r16431 (402fh) auxadc source 9 aux_wall_sel 0 auxadc wall input select 0 = disable wallvdd measurement 1 = enable wallvdd measurement 8 aux_batt_sel 0 auxadc batt input select 0 = disable battvdd measurement 1 = enable battvdd measurement 7 aux_usb_sel 0 auxadc usb input select 0 = disable usbvdd measurement 1 = enable usbvdd measurement 6 aux_sysvdd_s el 0 auxadc sysvdd input select 0 = disable sysvdd measurement 1 = enable sysvdd measurement 5 aux_batt_tem p_sel 0 auxadc battery temp input select 0 = disable battery temp measurement 1 = enable battery temp measurement 4 aux_chip_tem p_sel 0 auxadc chip temp input select 0 = disable chip temp measurement 1 = enable chip temp measurement 3 aux_aux4_sel 0 auxadcin4 input select 0 = disable auxadcin4 measurement 1 = enable auxadcin4 measurement 2 aux_aux3_sel 0 auxadcin3 input select 0 = disable auxadcin3 measurement 1 = enable auxadcin3 measurement 1 aux_aux2_sel 0 auxadcin2 input select 0 = disable auxadcin2 measurement 1 = enable auxadcin2 measurement 0 aux_aux1_sel 0 auxadcin1 input select 0 = disable auxadcin1 measurement 1 = enable auxadcin1 measurement table 65 auxadc control
WM8310 pre-production w pp, may 2012, rev 3.1 122 18.3 auxadc readback measured data from the auxadc is read via the auxadc data register (r16429), which contains two fields. the auxadc data source is indica ted in the aux_data_src field; the associated measurement data is contained in the aux_data field. reading from the auxadc data register returns a 12-bit code which represents the most recent auxadc measurement on the associated channel. it should be noted that every time an auxadc measurement is written to the auxadc data regist er, the previous data is overwritten - the host processor should ensure that data is read from this register before it is overwritten. the auxadc interrupts can be used to indicate when new data is available - see section 18.5. the 12-bit aux_data field can be equated to the act ual voltage (or temperature) according to the following equations, where aux_data is regarded as an unsigned integer: battery temperature measurement varies according to the selected ntc thermistor component. in a typical application, it is anticipated that the auxadc interrupts would be used to control the auxadc readback - the host processor should read t he auxadc data register in response to the auxadc interrupt event. see section 18.5 for details of auxadc interrupts. in automatic auxadc mode, the processor should complete this action before the next measurement occurs, in order to avoid losing any auxadc samples. in manual c onversion mode, the inte rrupt signal provides confirmation that the commanded measurement has been completed. the control fields associated with initia ting auxadc readback are defined in table 66. address bit label default description r16429 (402dh) auxadc data 15:12 aux_data_src [3:0] 000 auxadc data source 0 = reserved 1 = auxadcin1 2 = auxadcin2 3 = auxadcin3 4 = auxadcin4 5 = chip temperature 6 = battery temperature 7 = sysvdd voltage 8 = usb voltage 9 = batt voltage 10 = wall voltage 11 = reserved 12 = reserved 13 = reserved 14 = reserved 15 = reserved 11:0 aux_data [11:0] 000h auxadc measurement data voltage (mv) = aux_data x 1.465 chiptemp ( ? c) = (498 - aux_data) / 1.09 batttemp ( ? c) = (value is dependent on ntc thermistor) table 66 auxadc readback
pre-production WM8310 w pp, may 2012, rev 3.1 123 18.4 digital comparators the WM8310 has four digital comparators whic h may be used to compare auxadc measurement data against programmable threshold values. each comparator has a status bit, and also an associated interrupt flag (described in section 18. 5), which indicates that the associated data is beyond the threshold value. the digital comparators are enabled using the dcmpn_e na register bits as described in table 65. after an auxadc conversion, the measured value is compared with the threshold level of any associated comparator(s). note that this comparison is only performed following a conversion. the source data for each comparator is selected using the dcmp n_src register bits; this selects one of eight possible auxadc channels for each comparator. if required, the same auxadc channel may be selected for more than one comparator; this would allow more than one threshold to be monitored on the same auxadc channel. note that the coding of the 000b value of the dcmp n _src fields differs between the four comparators. the dcmp n _gt register bits select whether the st atus bit and associated interrupt flag will be asserted when the measured value is above the thre shold or when the measured value is below the threshold. the output of the most recent th reshold comparison is indicated in the dcomp n_sts fields. the threshold dcmp n _thr is a 12-bit code for each comparator . this field follows the same voltage or temperature coding as the associated auxadc channel source (see section 18.3). address bit label default description r16432 (4030h) comparator control 11 dcomp4_sts 0 digital comparator 4 status 0 = comparator 4 threshold not detected 1 = comparator 4 threshold detected (trigger is controlled by dcmp4_gt) 10 dcomp3_sts 0 digital comparator 3 status 0 = comparator 3 threshold not detected 1 = comparator 3 threshold detected (trigger is controlled by dcmp3_gt) 9 dcomp2_sts 0 digital comparator 2 status 0 = comparator 2 threshold not detected 1 = comparator 2 threshold detected (trigger is controlled by dcmp2_gt) 8 dcomp1_sts 0 digital comparator 1 status 0 = comparator 1 threshold not detected 1 = comparator 1 threshold detected (trigger is controlled by dcmp1_gt) 3 dcmp4_ena 0 digital comparator 4 enable 0 = disabled 1 = enabled 2 dcmp3_ena 0 digital comparator 3 enable 0 = disabled 1 = enabled 1 dcmp2_ena 0 digital comparator 2 enable 0 = disabled 1 = enabled 0 dcmp1_ena 0 digital comparator 1 enable 0 = disabled 1 = enabled r16433 (4031h) comparator 1 15:13 dcmp1_src [2:0] 000 digital comparator 1 source select 0 = usb voltage
WM8310 pre-production w pp, may 2012, rev 3.1 124 address bit label default description 1 = auxadcin1 2 = auxadcin2 3 = auxadcin3 4 = auxadcin4 5 = chip temperature 6 = battery temperature 7 = sysvdd voltage 12 dcmp1_gt 0 digital comparator 1 interrupt control 0 = interrupt when less than threshold 1 = interrupt when greater than or equal to threshold 11:0 dcmp1_thr 000h digital comparator 1 threshold (12-bit unsigned binary number; coding is the same as aux_data) r16434 (4032h) comparator 2 15:13 dcmp2_src [2:0] 000 digital comparator 2 source select 0 = wall voltage 1 = auxadcin1 2 = auxadcin2 3 = auxadcin3 4 = auxadcin4 5 = chip temperature 6 = battery temperature 7 = sysvdd voltage 12 dcmp2_gt 0 digital comparator 2 interrupt control 0 = interrupt when less than threshold 1 = interrupt when greater than or equal to threshold 11:0 dcmp2_thr 000h digital comparator 2 threshold (12-bit unsigned binary number; coding is the same as aux_data) r16435 (4033h) comparator 3 15:13 dcmp3_src [2:0] 000 digital comparator 3 source select 0 = batt voltage 1 = auxadcin1 2 = auxadcin2 3 = auxadcin3 4 = auxadcin4 5 = chip temperature 6 = battery temperature 7 = sysvdd voltage 12 dcmp3_gt 0 digital comparator 3 interrupt control 0 = interrupt when less than threshold 1 = interrupt when greater than or equal to threshold 11:0 dcmp3_thr 000h digital comparator 3 threshold (12-bit unsigned binary number; coding is the same as aux_data) r16436 (4034h) comparator 4 15:13 dcmp4_src [2:0] 000 digital comparator 4 source select 0 = reserved 1 = auxadcin1 2 = auxadcin2 3 = auxadcin3 4 = auxadcin4 5 = chip temperature 6 = battery temperature
pre-production WM8310 w pp, may 2012, rev 3.1 125 address bit label default description 7 = sysvdd voltage 12 dcmp4_gt 0 digital comparator 4 interrupt control 0 = interrupt when less than threshold 1 = interrupt when greater than or equal to threshold 11:0 dcmp4_thr 000h digital comparator 4 threshold (12-bit unsigned binary number; coding is the same as aux_data) table 67 auxadc digital comparator control 18.5 auxadc interrupts the auxadc is associated with a number of inte rrupt event flags to indicate when new auxadc data is ready, or to indicate that one or more of the digital comparator thresholds has been crossed. each of these secondary interrupts triggers a primary auxadc interrupt, auxadc_int (see section 23). this can be masked by setting t he mask bit(s) as described in table 68. note that auxadc_data_eint is not cleared by reading the measured auxadc data, it can only be cleared by writing ?1? to the auxadc_data_eint register. the auxadc interrupts can be progra mmed using bits in table 68. address bit label description r16401 (4011h) interrupt status 1 8 auxadc_data_eint auxadc data ready interrupt (rising edge triggered) note: cleared when a ?1? is written. 7:4 auxadc_dcomp n _eint auxadc digital comparator n interrupt (trigger is controlled by dcmp n_gt) note: cleared when a ?1? is written. r16409 (4019h) interrupt status 1 mask 8 im_auxadc_data_eint interrupt mask. 0 = do not mask interrupt. 1 = mask interrupt. default value is 1 (masked) 7:4 im_auxadc_dcomp n_ei nt interrupt mask. 0 = do not mask interrupt. 1 = mask interrupt. default value is 1 (masked) note: n is a number between 1 and 4 that identifies the individual comparator. table 68 auxadc interrupts 19 reserved
WM8310 pre-production w pp, may 2012, rev 3.1 126 20 real-time clock (rtc) 20.1 general description the WM8310 provides a real time clock (rtc) in the form of a 32-bit counter. the rtc uses the 32.768khz crystal oscillator as its clock source and increments the register value once per second. (note that a direct cmos input may be used in pl ace of the crystal oscillator; both options are described in section 13.) to compensate for erro rs in the clock frequency, the rtc includes a frequency trim capability. the rtc is enabled at all times, including when t he WM8310 is in the backup state. when required, the rtc can be maintained via a backup battery in the absence of any other power supply. in the absence of a backup battery, the rtc contents can be held (unclocked) for a limited period of up to 5 minutes via a 22 ? f capacitor. the rtc incorporates an alarm function. the alarm time is held in a 32-bit register. when the rtc counter matches the alarm time, a selectable response will be actioned. for digital rights management purposes, the rtc in cludes security features designed to detect unauthorised modifications to the rtc counter. 20.2 rtc control the 32-bit rtc counter value, rtc_time is held in two 16-bit registers, r16417 (4021h) and r16418 (4022h). the value of rtc_time is increm ented by the WM8310 once per second. on initial power-up (from the no power state), these registers will be initialised to default values. once either of these registers has been written to, the rtc_valid bit is set to indicate that the rtc_time registers contain valid data. when rtc registers are updated, the rtc_sync_busy bit indicates that the rtc is busy. the rtc registers should not be written to when rtc_sync_busy = 1. the rtc_wr_cnt field is provided as a security feature for the rtc. a fter initialisation, this field is updated on every write to r16417 (4021h) or to r 16418 (4022h). this enables the host processor to detect unauthorised modifications to the rtc counter value. see section 20.4 for more details. for additional security, the WM8310 does not allow the rtc to be updated more than 8 times in a one-hour period. additional write attempts will be ignored. the rtc alarm time is held in registers r 16419 (4023h) and r16420 (4024h). the alarm function is enabled when rtc_alm_ena is set. when the alarm is enabled, and the rtc counter matches the alarm time, the rtc alarm interrupt is triggered, as described in section 20.3. if the rtc alarm occurs in the sleep power stat e, then a wake transition request is generated. if the rtc alarm occurs in the off power state, then an on transition request is generated. see section 11.3 for details. when updating the rtc alarm time, it is reco mmended to disable the alarm first, by setting rtc_alm_ena = 0. the rtc alarm registers shoul d not be written to when rtc_sync_busy = 1. the rtc has a frequency trim feature to allow compensation for known and constant errors in the crystal oscillator frequency up to 8hz. the rtc_trim field is a 10-bit fixed point 2?s complement number. msb scaling = -8hz. to compensate for errors in the clock frequency, this register should be set to the error (in hz) with respect to t he ideal (32768hz) of the input crystal frequency. for example, if the actual crystal frequency = 32769.00hz, then the frequency error = +1hz. the value of rtc_trim in this case is 0001_000000. for example, if the actual crystal frequency = 32763.78hz, then the frequency error = -4.218750hz. the value of rtc_trim in this case is 1011_110010. note that the rtc_trim control register is lock ed by the WM8310 user key. this register can only be changed by writing the appropriate code to the secu rity register, as described in section 12.4.
pre-production WM8310 w pp, may 2012, rev 3.1 127 address bit label default description r16416 (4020h) rtc write counter 15:0 rtc_wr_cnt 0000h rtc write counter. this random number is updated on every write to the rtc_time registers. r16417 (4021h) rtc time 1 15:0 rtc_time [31:16] 0000h rtc seconds counter (msw) rtc_time increments by 1 every second. this is the 16 msbs. r16418 (4022h) rtc time 2 15:0 rtc_time [15:0] 0000h rtc seconds counter (lsw) rtc_time increments by 1 every second. this is the 16 lsbs. r16419 (4023h) rtc alarm 1 15:0 rtc_alm [31:16] 0000h rtc alarm time (msw) 16 msbs of rtc_alm r16420 (4024h) rtc alarm 2 15:0 rtc_alm [15:0] 0000h rtc alarm time (lsw) 16 lsbs of rtc_alm r16421 (4025h) rtc control 15 rtc_valid 0 rtc valid status 0 = rtc_time has not been set since power on reset 1 = rtc_time has been written to since power on reset 14 rtc_sync_bus y 0 rtc busy status 0 = normal 1 = busy the rtc registers should not be written to when rtc_sync_busy = 1. 10 rtc_alm_ena 0 rtc alarm enable 0 = disabled 1 = enabled r16422 (4026h) rtc trim 9:0 rtc_trim 000h rtc frequency trim. value is a 10bit fixed point <4,6> 2?s complement number. msb scaling = -8hz. the register indicates the error (in hz) with respect to the ideal 32768hz) of the input crystal frequency. protected by user key table 69 real time clock (rtc) control
WM8310 pre-production w pp, may 2012, rev 3.1 128 20.3 rtc interrupts the real time clock (rtc) is associ ated with two interrupt event flags. the rtc_per_eint interrupt is set each time a per iodic timeout occurs. the periodic timeout is configured using the rtc_pint_fre q field described in table 71. the rtc_alm_eint interrupt is set when the rt c alarm is triggered. the rtc alarm time is configured as described in section 20.2. each of these secondary interrupts triggers a pr imary real time clock interrupt, rtc_int (see section 23). this can be masked by setting t he mask bit(s) as described in table 70. address bit label description r16401 (4011h) interrupt status 1 3 rtc_per_eint rtc periodic interrupt (rising edge triggered) note: cleared when a ?1? is written. 2 rtc_alm_eint rtc alarm interrupt (rising edge triggered) note: cleared when a ?1? is written. r16409 (4019h) interrupt status 1 mask 3 im_rtc_per_eint interrupt mask. 0 = do not mask interrupt. 1 = mask interrupt. default value is 1 (masked) 2 im_rtc_alm_eint interrupt mask. 0 = do not mask interrupt. 1 = mask interrupt. default value is 1 (masked) table 70 real time clock (rtc) interrupts the frequency of the rtc periodic interrupts is set by the rtc_pint_freq field, as described in table 71. address bit label default description r16421 (4025h) rtc control 6:4 rtc_pint_freq [2:0] 000 rtc periodic interrupt timeout period 000 = disabled 001 = 2s 010 = 4s 011 = 8s 100 = 16s 101 = 32s 110 = 64s 111 = 128s table 71 real time clock (rtc) periodic interrupt control
pre-production WM8310 w pp, may 2012, rev 3.1 129 20.4 digital rights management the real time clock (rtc) maintains a continuous record of the time; this is maintained at all times, including when the WM8310 is powered down and the rtc function is maintained by the backup supply. it is highly desirable to be able to write to the rt c counter in order to configure it for logical translation into hours/minutes and to support cal endar functions. however, for digital rights management purposes, it is important that malicious modification of the rtc is either prevented or detected. the security measure implemented on the WM8310 is the rtc write counter. this register is initialised to 0000h during power on reset, and is updated automatically whenever a write operation is scheduled on either of the rtc_time registers. note that, when the rtc write counter is updated, the new value is generated at random; it is not a sequential counter. it is assumed that legitimate updates to the rtc_ time are only those initiated by the application processor (ap). when the ap makes an update to the rtc_time, the ap can also read the new value of the rtc write counter, and should store t he value in non-volatile memory. if the ap detects a change in value of the rtc write counter, and this was not caused by the ap itself writing to the rtc_time, this means that an unauthorised write to the rtc_time registers has occurred. in order to make it difficult for an unauthorised rtc_time update to be masked by simply writing to the rtc write counter, the rtc_wr_cnt fiel d is generated at random by the WM8310 whenever the rtc_time field is updated. for additional security, the WM8310 does not allow the rtc to be updated more than 8 times in a one-hour period. additional write attempts will be ignored. the rtc control registers are described in table 69. 20.5 backup mode clocking options the backup state is entered when the available power supplies are below the reset threshold of the device. typically, this means that usb or wall supp lies are not present and that the main battery is either discharged or removed. most of the device functions and registers are reset in this state. the rtc and oscillator and a ?software scratch? memory area can be maintained from a backup power source in the backup state. this is provided using a coin cell, super/gold capacitor, or else a standard capacitor, connected to the ldo12vout pin via a 22k ? resistor. see section 17.6 for further details. the rtc and oscillator can be disabled in the backu p state by setting the xtal_bkupena register bit to 0. this feature may be used to minimise t he device power consumption in the backup state. a 22? f capacitor connected to ldo12vout can mainta in the rtc value, unclocked, for up to 5 minutes in backup if the oscillator is disabled. the xtal_bkupena register bit is defined in sect ion 13.1. for more details on backup power, see section 17.6.
WM8310 pre-production w pp, may 2012, rev 3.1 130 21 general purpose inputs / outputs (gpio) 21.1 general description the WM8310 has 12 general-purpose input/output (g pio) pins, gpio1 - gpio12. these can be configured as inputs or outputs, ac tive high or active low, with optional on-chip pull-up or pull-down resistors. gpio outputs can either be cmos driven or open drain configurati on. each gpio pin can be tri-stated and can also be used to trigger interrupts. the function of each gpio pin is selected individually. different voltage power domains are selectable on a pin by pin basis. input de-bounce is automat ically implemented on selected gpio functions. 21.2 gpio functions the list of gpio functions supported by the WM8310 is contained in table 72 (for input functions) and table 73 (for output functions). the input f unctions are selected when the respective gp n_dir register bit is 1. the output functi ons are selected when the respective gp n_dir register bit is 0. the selected function for each gpio pin is selected by writing to the respective gp n_fn register bits. all functions are available on all gpio pins. the polarity of each i nput or output gpio function can be selected using the applicable gp n_pol register bit. the available power domains for each pi n are specific to different gpios. the de-bounce time for the gpio i nput functions is determined by t he gpn_fn field. some of the input functions allow a choice of de- bounce times, as detailed in table 72. the register controls for configuring t he gpio pins are defined in section 21.3. gpn_fn gpio input function description de-bounce time 0h gpio gpio input. logic level is read from the gpn_lvl register bits. see section 21.3. 32? s to 64 ? s 1h 4ms to 8ms 2h on/off request control input for requesting an on/off state transition. see section 11.3. under default polarity (gpn_pol=1), a rising edge requests the on state and a falling edge requests the off state. 32ms 64ms 3h sleep/wake request control input for requesting a sleep/wake state transition. see section 11.3. under default polarity (gpn_pol=1), a rising edge requests the sleep state and a falling edge requests the wake transition to the on state. 32? s to 64 ? s 4h 32ms to 64ms 5h sleep request control input for requesting a sleep state transition. see section 11.3. under default polarity (gpn_pol=1), a rising edge requests the sleep state and a falling edge has no effect. 32? s to 64 ? s 6h on request control input for requesting an on state transition. see section 11.3. under default polarity (gpn_pol=1), a rising edge requests the on state and a falling edge has no effect. 32? s to 64 ? s 7h watchdog reset control input for resetting the watchdog timer. see section 25. 32? s to 64 ? s 8h hardware dvs control 1 control input for selecting the dvs output voltage in one or more dc-dc converters. see section 15.6. none 9h hardware dvs control 2 control input for selecting the dvs output voltage in one or more dc-dc converters. see section 15.6. none
pre-production WM8310 w pp, may 2012, rev 3.1 131 gpn_fn gpio input function description de-bounce time ah hardware enable 1 control input for enabling one or more dc-dc converters and ldo regulators. see section 15. 32? s to 64 ? s bh hardware enable 2 control input for enabling one or more dc-dc converters and ldo regulators. see section 15. 32? s to 64 ? s ch hardware control input 1 control input for selecting the operating mode and/or output voltage of one or more dc-dc converters and ldo regulators. see section 15. 32? s to 64 ? s dh hardware control input 2 control input for selecting the operating mode and/or output voltage of one or more dc-dc converters and ldo regulators. see section 15. 32? s to 64 ? s eh hardware control input 1 control input for selecting the operating mode and/or output voltage of one or more dc-dc converters and ldo regulators. see section 15. 32ms to 64ms fh hardware control input 2 control input for selecting the operating mode and/or output voltage of one or more dc-dc converters and ldo regulators. see section 15. 32ms to 64ms table 72 list of gpio input functions further details of the gpio input de-bounce time are noted in section 21.3. gpn_fn gpio output function description 0h gpio gpio output. logic level is set by writing to the gpn_lvl register bits. see section 21.3. 1h oscillator clock 32.768khz clock output. see section 13. 2h on state logic output indicating that the WM8310 is in the on state. see section 11.5. 3h sleep state logic output indicating that the WM8310 is in the sleep state. see section 11.5. 4h power state change logic output asserted whenever a power on reset, or an on, off, sleep or wake transition has completed. under default polarity (gp n_pol=1), the logic level is the same as the ps_int interrupt status flag. note that, if any of the associated secondary interrupts is masked, then the respective event will not affect the power state change gpio output. see section 11.2 and section 11.4. 8h dc-dc1 dvs done logic output indicating that dc-dc1 buck converter dvs slew has been completed. this signal is temporarily de-asserted during voltage transitions (incl uding non-dvs transitions). see section 15.6. 9h dc-dc2 dvs done logic output indicating that dc-dc1 buck converter dvs slew has been completed. this signal is temporarily de-asserted during voltage transitions (incl uding non-dvs transitions). see section 15.6. ah external power enable 1 logic output assigned to one of the timeslots in the on/off and sleep/wake sequences. this can be used for sequenced control of external circuits. see section 15.3. bh external power enable 2 logic output assigned to one of the timeslots in the on/off and sleep/wake sequences. this can be used for sequenced control of external circuits. see section 15.3.
WM8310 pre-production w pp, may 2012, rev 3.1 132 gpn_fn gpio output function description ch system supply good (sysvdd good) logic output from sysvdd monito ring circuit. this function represents the internal sysok signal. see section 24.4. dh converter power good (pwr_good) status output indicating that all selected dc-dc converters and ldo regulators are operating correctly. only asserted in on and sleep modes. see section 15.14. eh external power clock 2mhz clock output suitable for clocking external dc-dc converters. this clock signal is synchronized with the WM8310 dc-dc converters clocking signal. see section 13. this clock output is only enabled when either of the external power enable signals (epe1 or epe2) is asserted. these signals can be assigned to one of the timeslots in the on/off and sleep/wake sequences. see section 15.3. fh auxiliary reset logic output indicating a reset condition. this signal is asserted in the off state. the status in sleep mode is configurable. see section 11.7. note that the default polarity for this function (gp n_pol=1) is ?active high?. setting gp n _pol=0 will select ?active low? function. table 73 list of gpio output functions 21.3 configuring gpio pins the gpio pins are confi gured using the resister fi elds defined in table 74. the function of each gpio is selected using the gpn_fn register field. the pin direction field gpn_dir selects between input functions and output functions. see section 21.2 for a summary of the available gpio functions. the polarity of each gpio can be c onfigured using the gpn_pol bits. th is inversion is effective both on gpio inputs and outputs. when gpn_pol = 1, the non-inverted ?active high? polarity applies. the opposite logic can be selected by setting gpn_pol = 0. the voltage power domain of each gpio is determi ned by the gpn_pwr_dom register. note that the available options vary between different gpio pins, as described in table 76. a gpio output may be either cmos driven or open drain. this is selected using the gpn_od bits. internal pull-up or pull-down resistors can be enabled on each pin using the gpn_pull field. both resistors are available for use when the associ ated gpio is an input. when the gpio pin is configured as an open drain output, the internal pull- up resistor may be required if no external pull-up resistors are present. the gpio pins may be enabled or tri-stated using t he gpn_ena register field. when gpn_ena = 0, the respective pin is tri-stated. a tri-stated pin exhibits high impedance to any external circuit and is disconnected from the internal gp io circuits. the pull-up and pull-dow n resistors are disabled when a gpio pin is tri-stated. gpio pins can generate an interrupt (see section 21.4). the gp n _int_mode field selects whether the interrupt occurs on a single edge only, or else on both rising and falling edges. when single edge is selected, the active edge is the rising edge (when gpn_pol = 1) or the falling edge (when gpn_pol = 0.
pre-production WM8310 w pp, may 2012, rev 3.1 133 address bit label default description r16440 (4038h) to r16451 (4043h) 15 gpn_dir 1 gpio n pin direction 0 = output 1 = input 14:13 gpn_pull [1:0] 01 gpio n pull-up / pull-down configuration 00 = no pull resistor 01 = pull-down enabled 10 = pull-up enabled 11 = reserved 12 gpn_int_m ode 0 gpio n interrupt mode 0 = gpio interrupt is rising edge triggered (if gp n_pol=1) or falling edge triggered (if gp n_pol =0) 1 = gpio interrupt is triggered on rising and falling edges 11 gpn_pwr_d om 0 gpio n power domain see table 76. 10 gpn_pol 1 gpio n polarity select 0 = inverted (active low) 1 = non-inverted (active high) 9 gpn_od 0 gpio n output pin configuration 0 = cmos 1 = open drain 7 gpn_ena 0 gpio n enable control 0 = gpio pin is tri-stated 1 = normal operation 3:0 gp n_fn [3:0] 0000 gpio n pin function see table 77. note: n is a number between 1 and 12 that identifies the individual gpio. note: the default values noted are valid when the WM8310 powers up to the off state, or if the register map is reset following a device reset or software reset event. in the case of gpio pins 1 to 6, these registers are overwritten with the respective ice or otp memory contents when an on transition is scheduled. table 74 gpio pin configuration when the gpio output function is selected (gpn_fn = 0h, gpn_dir = 0), the state of a gpio output is controlled by writing to the corresponding gp n_lvl register bit, as defined in table 75. the logic level of a gpio input is determined by reading the corresponding gp n_lvl register bit. if gpn_pol is set, then the read value of the gpn_lvl field for a gpio input is the inverse of the external signal. note that, when the gpio input level changes, the logic level of gpn_lvl will only be updated after the maximum de-bounce period, as listed in table 72. an input pulse that is shorter than the minimum de-bounce period will be filter ed by the de-bounce function and will be ignored. if a gpio is configured as a cm os output (ie. gpn_od = 0), then the read value of the gpn_lvl field will indicate the logic level of that output. if gp n_pol is set, then the read value of the gp n_lvl field for a gpio output is the inverse of the level on the external pad. if a gpio is configured as an open drain output, then the read value of gpn_lvl is only valid when the internal pull-up resistor is enabled on the pin (ie. when gpn_pull = 10). the read value is also affected by the gpn_pol bit, as described above for the cmos case. if a gpio is tri-stated (gp n_ena = 0), then the read value of the corresponding gpn_lvl field is invalid.
WM8310 pre-production w pp, may 2012, rev 3.1 134 address bit label default description r16396 (400ch) gpio level 11 gp12_lvl 0 gpio n level. when gp n_fn = 0h and gp n_dir = 0, write to this bit to set a gpio output. read from this bit to read gpio input level. when gp n_pol is 0, the register contains the opposite logic level to the external pin. write to this bit to set a gpio output. 10 gp11_lvl 0 9 gp10_lvl 0 8 gp9_lvl 0 7 gp8_lvl 0 6 gp7_lvl 0 5 gp6_lvl 0 4 gp5_lvl 0 3 gp4_lvl 0 2 gp3_lvl 0 1 gp2_lvl 0 0 gp1_lvl 0 table 75 gpio level register the power domain for each gpio is controlled us ing the gpn_pwr_dom registers as described in table 76. address bit label default description r16440 (4038h) gpio1 control 11 gp1_pwr_do m 0 gpio1 power domain select 0 = dbvdd 1 = vpmic (ldo12) r16441 (4039h) gpio2 control 11 gp2_pwr_do m 0 gpio2 power domain select 0 = dbvdd 1 = vpmic (ldo12) r16442 (403ah) gpio3 control 11 gp3_pwr_do m 0 gpio3 power domain select 0 = dbvdd 1 = vpmic (ldo12) r16443 (403bh) gpio4 control 11 gp4_pwr_do m 0 gpio4 power domain select 0 = dbvdd 1 = sysvdd r16444 (403ch) gpio5 control 11 gp5_pwr_do m 0 gpio5 power domain select 0 = dbvdd 1 = sysvdd r16445 (403dh) gpio6 control 11 gp6_pwr_do m 0 gpio6 power domain select 0 = dbvdd 1 = sysvdd r16446 (403eh) gpio7 control 11 gp7_pwr_do m 0 gpio7 power domain select 0 = dbvdd 1 = vpmic (ldo12) r16447 (403fh) gpio8 control 11 gp8_pwr_do m 0 gpio8 power domain select 0 = dbvdd 1 = vpmic (ldo12) r16448 (4040h) gpio9 control 11 gp9_pwr_do m 0 gpio9 power domain select 0 = dbvdd 1 = vpmic (ldo12) r16449 (4041h) gpio10 control 11 gp10_pwr_d om 0 gpio10 power domain select 0 = dbvdd 1 = sysvdd r16450 (4042h) gpio11 control 11 gp11_pwr_d om 0 gpio11 power domain select 0 = dbvdd 1 = sysvdd
pre-production WM8310 w pp, may 2012, rev 3.1 135 address bit label default description r16451 (4043h) gpio12 control 11 gp12_pwr_d om 0 gpio12 power domain select 0 = dbvdd 1 = sysvdd table 76 gpio power domain registers the function of each gpio is cont rolled using the gpn_fn registers defined in table 77. note that the selected function also depends on the associ ated gpn_dir field described in table 74. see also section 21.2 for additional details of eac h gpio function, including the applicable de-bounce times for gpio input functions. address bit label default description r16440 (4038h) gpio1 control 3:0 gp1_fn [3:0] 0000 input functions: 0h = gpio input (long de-bounce) 1h = gpio input 2h = power on/off request 3h = sleep/wake request 4h = sleep/wake request (long de- bounce) 5h = sleep request 6h = power on request 7h = watchdog reset input 8h = dvs1 input 9h = dvs2 input ah = hw enable1 input bh = hw enable2 input ch = hw control1 input dh = hw control2 input eh = hw control1 input (long de- bounce) fh = hw control2 input (long de- bounce) output functions: 0h = gpio output 1h = 32.768khz oscillator output 2h = on state 3h = sleep state 4h = power state change 5h = reserved 6h = reserved 7h = reserved 8h = dc-dc1 dvs done 9h = dc-dc2 dvs done ah = external power enable1 bh = external power enable2 ch = system supply good (sysok) dh = converter power good (pwr_good) eh = external power clock (2mhz) fh = auxiliary reset r16441 (4039h) gpio2 control 3:0 gp2_fn [3:0] 0000 r16442 (403ah) gpio3 control 3:0 gp3_fn [3:0] 0000 r16443 (403bh) gpio4 control 3:0 gp4_fn [3:0] 0000 r16444 (403ch) gpio5 control 3:0 gp5_fn [3:0] 0000 r16445 (403dh) gpio6 control 3:0 gp6_fn [3:0] 0000 r16446 (403eh) gpio7 control 3:0 gp7_fn [3:0] 0000 r16447 (403fh) gpio8 control 3:0 gp8_fn [3:0] 0000 r16448 (4040h) gpio9 control 3:0 gp9_fn [3:0] 0000 r16449 (4041h) gpio10 control 3:0 gp10_fn [3:0] 0000 r16450 (4042h) gpio11 control 3:0 gp11_fn [3:0] 0000 r16451 (4043h) gpio12 control 3:0 gp12_fn [3:0] 0000 table 77 gpio function select registers
WM8310 pre-production w pp, may 2012, rev 3.1 136 note that gpio input functions 2h, 3h, 4h, 5h and 6h are edge-triggered only. the associated state transition(s) are scheduled only when a rising or falli ng edge is detected on the respective gpio pin. at other times, it is possible that other state tr ansition events may cause a state transition regardless of the state of the gpio input. see section 11.3 for details of all the state transition events. note that sleep transitions are not possible when any of the battery charger interrupts is set. if any of the battery charger interrupts is asserted when a sleep transition is requested, then the transition will be unsuccessful and the WM8310 will remain in the on power state. see section 17.7.8 for details of the battery charger interrupts. 21.4 gpio interrupts each gpio pin has an associated interrupt flag, gp n_eint, in register r16405 (4015h). each of these secondary interrupts triggers a primary gpio interrupt, gp_int (see section 23). this can be masked by setting the mask bit(s) as described in table 78. see section 28 and section 29 for a definition of t he register bit positions applicable to each gpio. address bit label description r16405 (4015h) interrupt status 5 11:0 gp n_eint gpio interrupt. (trigger is controlled by gp n_int_mode) note: cleared when a ?1? is written. r16413 (401dh) interrupt status 5 mask 11:0 im_gp n_eint interrupt mask. 0 = do not mask interrupt. 1 = mask interrupt. default value is 1 (masked) note: n is a number between 1 and 12 that identifies the individual gpio. table 78 gpio interrupts
pre-production WM8310 w pp, may 2012, rev 3.1 137 22 system status led drivers 22.1 general description the WM8310 provides two system status led driver s. these are digital outputs intended for driving leds directly. the led outputs can be assigned to i ndicate otp program status, power state status or battery charger status. they can also be comm anded directly via register control, in order to provide any other required functionality. 22.2 led driver control led drivers are configurable in the on and sleep pow er states only. the functionality of the led drivers is controlled by the ledn_src r egister bits, as described in table 79. address bit label default description r16460 (404ch) status led1 15:14 led1_src [1:0] 11 led1 source (selects the led1 function.) 00 = off 01 = power state status 10 = charger status 11 = manual mode note: led1 also indicates completion of otp auto program r16461 (404dh) status led2 15:14 led2_src [1:0] 11 led2 source (selects the led2 function.) 00 = off 01 = power state status 10 = charger status 11 = manual mode note: led2 also indicates an otp auto program error condition table 79 system status led control 22.2.1 otp program status the led drivers indicate the status of the otp auto program function, where the contents of the external instantconfig? (ice) memory are automatically programmed into the otp. see section 14.6.3 for further details of the otp auto program function. when the otp auto program function is executed, the system status led drivers follow the functionality defined in table 80. led driver description drive mode led ?on? time on:off duty cycle led1 otp auto program complete constant n/a n/a led2 otp auto progam error constant n/a n/a table 80 system status led outputs - otp program status the otp program status led outputs will continue until a device reset. note that the otp program status is always indicated via the led outputs, regardless of the ledn_src register fields.
WM8310 pre-production w pp, may 2012, rev 3.1 138 22.2.2 power state status setting ledn_src = 01 configures the associated led to indicate power state status. under this selection, four different conditions ma y be indicated, as defined in table 81. led driver description drive mode led ?on? time on:off duty cycle led1 or led2 power sequence failure pulsed sequence (4 pulses) 1s 1:1 sysvdd low continuous pulsed 250ms 1:3 on state constant n/a n/a sleep state continuous pulsed 250ms 1:7 table 81 system status led outputs - power state status if more than one of the conditions listed occurs simultaneously, then the led output pattern is controlled by the condition in the hi ghest position within the list above. for example, if the sysvdd low condition occurs while in the on or sleep states, then the led output follows the pattern defined for the sysvdd low condition. the sysvdd low indication is asserted if sysv dd is less than the use r-selectable threshold syslo_thr, as described in section 24.4. note that, in the case of power sequence failure, the transition to off occurs after the 4 led pulses have been emitted. 22.2.3 charger status setting ledn_src = 10 configures the associated led to indicate battery charger status. under this selection, two different conditions may be indicated, as defined in table 82. led driver description drive mode led ?on? time on:off duty cycle led1 or led2 charger complete constant n/a n/a charger on continuous pulsed 1s 1:2 table 82 system status led outputs - charger status 22.2.4 led driver manual mode setting ledn_src = 11 configures the associated le d to operate in manual mode, which is further configurable using additional register fields. in manual mode, the led output can be commanded as off, on (constant), continuous pulsed or pulsed sequence. the selected operation is determi ned by the ledn_mode registers as described in table 83. in continuous pulsed mode and pulsed sequence mode, the ?on? time and the duty cycle can be configured using the ledn_dur and led n_duty_cyc registers respectively. in pulsed sequence mode, the number of pulse s in the sequence can be selected using the ledn_seq_len register. on completion of the commanded number of pulses, the led remains off until ledn_mode or ledn_src is changed to another value.
pre-production WM8310 w pp, may 2012, rev 3.1 139 address bit label default description r16460 (404ch) status led1 9:8 led1_mode [1:0] 00 led1 mode (controls led1 in manual mode only.) 00 = off 01 = constant 10 = continuous pulsed 11 = pulsed sequence 5:4 led1_seq_le n [1:0] 10 led1 pulse sequence length (when led1_mode = pulsed sequence) 00 = 1 pulse 01 = 2 pulses 10 = 4 pulses 11 = 7 pulses 3:2 led1_dur [1:0] 01 led1 on time (when led1_mode = continuous pulsed or pulsed sequence) 00 = 1 second 01 = 250ms 10 = 125ms 11 = 62.5ms 1:0 led1_duty_c yc [1:0] 10 led1 duty cycle (on:off ratio) (when led1_mode = continuous pulsed or pulsed sequence) 00 = 1:1 (50% on) 01 = 1:2:(33.3% on) 10 = 1:3 (25% on) 11 = 1:7 (12.5% on) r16461 (404dh) status led2 9:8 led2_mode [1:0] 00 led2 mode (controls led2 in manual mode only.) 00 = off 01 = constant 10 = continuous pulsed 11 = pulsed sequence 5:4 led2_seq_le n [1:0] 10 led2 pulse sequence length (when led2_mode = pulsed sequence) 00 = 1 pulse 01 = 2 pulses 10 = 4 pulses 11 = 7 pulses 3:2 led2_dur [1:0] 01 led2 on time (when led2_mode = continuous pulsed or pulsed sequence) 00 = 1 second 01 = 250ms 10 = 125ms 11 = 62.5ms 1:0 led2_duty_c yc [1:0] 10 led2 duty cycle (on:off ratio) (when led2_mode = continuous pulsed or pulsed sequence) 00 = 1:1 (50% on) 01 = 1:2:(33.3% on) 10 = 1:3 (25% on) 11 = 1:7 (12.5% on) table 83 system status led outputs - manual mode control
WM8310 pre-production w pp, may 2012, rev 3.1 140 22.3 led driver connections the recommended connection for system status leds is illustrated in figure 28. the led outputs are referenced to the sysvdd power domain. a series resistor may be required, depending on the led characteristics and the sysvdd voltage. WM8310 led1 sysvdd gnd figure 28 system status led connections
pre-production WM8310 w pp, may 2012, rev 3.1 141 23 interrupt controller the WM8310 has a comprehensive interrupt logic capability. the dedicated irq pin can be used to alert a host processor to selected events or fault conditions. each of the interrupt conditions can be individually enabled or masked. following an interr upt event, the host processor should read the interrupt registers in order to determine what caused the interrupt, and take appropriate action if required. the WM8310 interrupt controller has two levels: secondary interrupts indicate a single event in one of the circuit blocks. the event is indicated by setting a register bit. this bit is a latching bit - once it is set, it rema ins at logic 1 even if the trigger condition is cleared. the secondary in terrupts are cleared by writing a logic 1 to the relevant register bit. note that reading the register does not clear the secondary interrupt. primary interrupts are the logical or of the associated secondary interrupts (usually all the interrupts associated with one particular circuit block). each of the secondary interrupts can be individually masked or enabled as an input to the corresponding prim ary interrupt. the primary interrupt register r16400 (4010h) is read-only. the status of the irq pin reflects the logical nor of the pr imary interrupts. a logic 0 indicates that one or more of the primary interrupts is asserted. each of the primary interrupts can be individually masked or enabled as an input to the irq pin output. the irq pin output can either be cmos driven or o pen drain (integrated pull-up) configuration, as determined by the irq_od register bit. when the irq pin is open drain, it is actively driven low when asserted; the pull-up causes a logic high output when not asserted. the open drain configuration enables multiple devices to share a common interrupt line with the host processor. the irq pin output can be masked by setting t he im_irq register bit. when the irq pin is masked, it is held in the logic 1 (or open drain) state regardless of any internal interrupt event. note that the secondary interrupt bits are always valid - they are set as normal, regardless of whether the bit is enabled or masked as an input to the co rresponding primary interrupt. the primary interrupt bits are set and cleared as normal in response to any unmasked secondary interrupt, regardless of whether the primary interrupt bit is enabled or masked as an input to the irq pin output. note also that if any internal condition is configur ed to trigger an event other than an interrupt (eg. the watchdog timer triggers reset), these events are al ways actioned, regardless of the state of any interrupt mask bits. the irq pin output is configured using the register bits described in table 84. address bit label description r16407 (4017h) irq config 1 irq_od irq pin configuration 0 = cmos 1 = open drain (integrated pull-up) 0 im_irq irq pin output mask 0 = normal 1 = irq output is masked table 84 irq pin configuration
WM8310 pre-production w pp, may 2012, rev 3.1 142 the interrupt logic is illustrated in figure 29. event-level register bit (read only) e.g. rtc_alm_eint event / fault condition sets secondary interrupt e.g. rtc alarm ?mask? register bit (read/write) e.g. im_rtc_alm_eint writing ?1? to this bit clears the secondary interrupt and or other secondary interrupts e.g. rtc_per_eint nor irq pin other primary interrupts e.g. chg_int, auxadc_int and ?mask? register bit (read/write) e.g. im_rtc_int primary interrupt register bit (read only) e.g. rtc_int or irq mask bit im_irq figure 29 interrupt logic following the assertion of the irq pin to indicate an interrupt ev ent, the host processor can determine which primary interrupt caused the event by r eading the primary interrupt register r16400 (4010h). this register is defined in section 23.1. after reading the primary interrupt register, the host processor must read the corresponding secondary interrupt register(s) in order to determine which specific event caused the irq pin to be asserted. the host processor clears the secondary in terrupt bit by writing a logic 1 to that bit. 23.1 primary interrupts the primary interrupts are defined in table 85. thes e bits are read only. they are set when any of the associated unmasked secondary interrupts is set. they can only be reset when all of the associated secondary resets are cleared or masked. each primary interrupt can be masked. when a mask bit is set, the corresponding primary interrupt is masked and does not cause the irq pin to be asserted. the primary interrupt bits in r16408 (4018h) are valid regardless of whether the mask bit is se t. the primary interrupts are all masked by default. address bit label description r16400 (4010h) system interrupts 15 ps_int power state primary interrupt 0 = no interrupt 1 = interrupt is asserted 14 temp_int thermal primary interrupt 0 = no interrupt 1 = interrupt is asserted 13 gp_int gpio primary interrupt 0 = no interrupt 1 = interrupt is asserted 12 on_pin_int on pin primary interrupt 0 = no interrupt 1 = interrupt is asserted 11 wdog_int watchdog primary interrupt 0 = no interrupt 1 = interrupt is asserted 8 auxadc_int auxadc primary interrupt 0 = no interrupt 1 = interrupt is asserted 7 ppm_int power path management primary interrupt 0 = no interrupt
pre-production WM8310 w pp, may 2012, rev 3.1 143 address bit label description 1 = interrupt is asserted 6 cs_int current sink primary interrupt 0 = no interrupt 1 = interrupt is asserted 5 rtc_int real time clock primary interrupt 0 = no interrupt 1 = interrupt is asserted 4 otp_int otp memory primary interrupt 0 = no interrupt 1 = interrupt is asserted 2 chg_int battery charger primary interrupt 0 = no interrupt 1 = interrupt is asserted 1 hc_int high current primary interrupt 0 = no interrupt 1 = interrupt is asserted 0 uv_int undervoltage primary interrupt 0 = no interrupt 1 = interrupt is asserted r16408 (4018h) system interrupts mask 15 im_ps_int interrupt mask. 0 = do not mask interrupt. 1 = mask interrupt. default value is 1 (masked) 14 im_temp_int interrupt mask. 0 = do not mask interrupt. 1 = mask interrupt. default value is 1 (masked) 13 im_gp_int interrupt mask. 0 = do not mask interrupt. 1 = mask interrupt. default value is 1 (masked) 12 im_on_pin_int interrupt mask. 0 = do not mask interrupt. 1 = mask interrupt. default value is 1 (masked) 11 im_wdog_int interrupt mask. 0 = do not mask interrupt. 1 = mask interrupt. default value is 1 (masked) 8 im_auxadc_int interrupt mask. 0 = do not mask interrupt. 1 = mask interrupt. default value is 1 (masked) 7 im_ppm_int interrupt mask. 0 = do not mask interrupt. 1 = mask interrupt. default value is 1 (masked) 6 im_cs_int interrupt mask. 0 = do not mask interrupt. 1 = mask interrupt. default value is 1 (masked) 5 im_rtc_int interrupt mask. 0 = do not mask interrupt. 1 = mask interrupt.
WM8310 pre-production w pp, may 2012, rev 3.1 144 address bit label description default value is 1 (masked) 4 im_otp_int interrupt mask. 0 = do not mask interrupt. 1 = mask interrupt. default value is 1 (masked) 2 im_chg_int interrupt mask. 0 = do not mask interrupt. 1 = mask interrupt. default value is 1 (masked) 1 im_hc_int interrupt mask. 0 = do not mask interrupt. 1 = mask interrupt. default value is 1 (masked) 0 im_uv_int interrupt mask. 0 = do not mask interrupt. 1 = mask interrupt. default value is 1 (masked) table 85 primary interrupt status and mask bits 23.2 secondary interrupts the following sections define the secondary interrupt status and control bits associated with each of the primary interrupt bits defined in table 85. 23.2.1 power state interrupt the primary ps_int interrupt comprises three secondary interrupts as described in section 11.4. the secondary interrupt bits are defined in table 86. each of the secondary interrupts can be masked. when a mask bit is set, the corresponding interrupt event is masked and does not trigger a ps_int in terrupt. the secondary interrupt bits in r16402 (4012h) are valid regardless of w hether the mask bit is set. the se condary interrupts are all masked by default. address bit label description r16402 (4012h) interrupt status 2 2 ps_por_eint power on reset interrupt (rising edge triggered) note: cleared when a ?1? is written. 1 ps_sleep_off_eint sleep or off interrupt (rising edge triggered) note: cleared when a ?1? is written. 0 ps_on_wake_eint on or wake interrupt (rising edge triggered) note: cleared when a ?1? is written. r16410 (401ah) interrupt status 2 mask 2 im_ps_por_eint interrupt mask. 0 = do not mask interrupt. 1 = mask interrupt. default value is 1 (masked) 1 im_ps_sleep_off_eint interrupt mask. 0 = do not mask interrupt. 1 = mask interrupt. default value is 1 (masked) 0 im_ps_on_wake_eint interrupt mask. 0 = do not mask interrupt. 1 = mask interrupt. default value is 1 (masked) table 86 power state interrupts
pre-production WM8310 w pp, may 2012, rev 3.1 145 23.2.2 thermal interrupts the primary temp_int interrupt comprises a singl e secondary interrupt as described in section 26. the secondary interrupt bit is defined in table 87. the secondary interrupt can be masked. when the ma sk bit is set, the corresponding interrupt event is masked and does not trigger a temp_int interr upt. the secondary interrupt bit in r16401 (4011h) is valid regardless of whether the mask bit is set. the secondary interrupt is masked by default. address bit label description r16401 (4011h) interrupt status 1 1 temp_thw_cint thermal warning interrupt (rising and falling edge triggered) note: cleared when a ?1? is written. r16410 (4019h) interrupt status 1 mask 1 im_temp_thw_cint interrupt mask. 0 = do not mask interrupt. 1 = mask interrupt. default value is 1 (masked) table 87 thermal interrupts 23.2.3 gpio interrupts the primary gp_int interrupt comprises twelve secondary interrupts as described in section 21.4. the secondary interrupt bits are defined in table 88. each of the secondary interrupts can be masked. when a mask bit is set, the corresponding interrupt event is masked and does not trigger a gp_int in terrupt. the secondary interrupt bits in r16405 (4015h) are valid regardless of w hether the mask bit is set. the se condary interrupts are all masked by default. address bit label description r16405 (4015h) interrupt status 5 11:0 gp n_eint gpio interrupt. (trigger is controlled by gp n_int_mode) note: cleared when a ?1? is written. r16413 (401dh) interrupt status 5 mask 11:0 im_gp n_eint interrupt mask. 0 = do not mask interrupt. 1 = mask interrupt. default value is 1 (masked) note: n is a number between 1 and 12 that identifies the individual gpio. table 88 gpio interrupts 23.2.4 on pin interrupts the primary on_pin_int interrupt comprises a single secondary interrupt as described in section 11.6. the secondary interrupt bit is defined in table 89. the secondary interrupt can be masked. when the ma sk bit is set, the corresponding interrupt event is masked and does not trigger an on_pin_int in terrupt. the secondary interrupt bit in r16401 (4011h) is valid regardless of whether the mask bit is set. the secondary interrupt is masked by default.
WM8310 pre-production w pp, may 2012, rev 3.1 146 address bit label description r16401 (4011h) interrupt status 1 12 on_pin_cint on pin interrupt. (rising and falling edge triggered) note: cleared when a ?1? is written. r16409 (4019h) interrupt status 1 mask 12 im_on_pin_cint interrupt mask. 0 = do not mask interrupt. 1 = mask interrupt. default value is 1 (masked) table 89 on pin interrupt 23.2.5 watchdog interrupts the primary wdog_int interrupt comprises a single secondary interrupt as described in section 25. the secondary interrupt bits are defined in table 90. the secondary interrupt can be masked. when the ma sk bit is set, the corresponding interrupt event is masked and does not trigger a wdog_int interrupt. the secondary interrupt bit in r16401 (4011h) is valid regardless of whether the mask bit is set. the secondary interrupt is masked by default. address bit label description r16401 (4011h) interrupt status 1 11 wdog_to_eint watchdog timeout interrupt. (rising edge triggered) note: cleared when a ?1? is written. r16409 (4019h) interrupt status 1 mask 11 im_wdog_to_eint interrupt mask. 0 = do not mask interrupt. 1 = mask interrupt. default value is 1 (masked) table 90 watchdog timer interrupts 23.2.6 reserved 23.2.7 reserved 23.2.8 auxadc interrupts the primary auxadc_int interrupt comprises five secondary interrupts as described in section 18.5. the secondary interrupt bits are defined in table 91. each of the secondary interrupts can be masked. when a mask bit is set, the corresponding interrupt event is masked and does not trigger a auxadc_in t interrupt. the secondary interrupt bits in r16401 (4011h) are valid regardless of whether the mask bit is set. the secondary interrupts are all masked by default. address bit label description r16401 (4011h) interrupt status 1 8 auxadc_data_eint auxadc data ready interrupt (rising edge triggered) note: cleared when a ?1? is written. 7:4 auxadc_dcomp n _eint auxadc digital comparator n interrupt (trigger is controlled by dcmp n_gt) note: cleared when a ?1? is written. r16409 (4019h) interrupt status 1 mask 8 im_auxadc_data_eint interrupt mask. 0 = do not mask interrupt. 1 = mask interrupt. default value is 1 (masked)
pre-production WM8310 w pp, may 2012, rev 3.1 147 address bit label description 7:4 im_auxadc_dcomp n_ei nt interrupt mask. 0 = do not mask interrupt. 1 = mask interrupt. default value is 1 (masked) note: n is a number between 1 and 4 that identifies the individual comparator. table 91 auxadc interrupts 23.2.9 power path management interrupts the primary ppm_int interrupt co mprises three secondary interrupts as described in section 17.5. the secondary interrupt bits are defined in table 92. each of the secondary interrupts can be masked. when a mask bit is set, the corresponding interrupt event is masked and does not trigger a ppm_int in terrupt. the secondary interrupt bits in r16401 (4011h) are valid regardless of w hether the mask bit is set. the se condary interrupts are all masked by default. address bit label description r16401 (4011h) interrupt status 1 15 ppm_syslo_eint power path syslo interrupt (rising edge triggered) note: cleared when a ?1? is written. 14 ppm_pwr_src_eint power path source interrupt (rising edge triggered) note: cleared when a ?1? is written. 13 ppm_usb_curr_eint power path usb current interrupt (rising edge triggered) note: cleared when a ?1? is written. r16409 (4019h) interrupt status 1 mask 15 im_ppm_syslo_eint interrupt mask. 0 = do not mask interrupt. 1 = mask interrupt. default value is 1 (masked) 14 im_ppm_pwr_src_eint interrupt mask. 0 = do not mask interrupt. 1 = mask interrupt. default value is 1 (masked) 13 im_ppm_usb_curr_ein t interrupt mask. 0 = do not mask interrupt. 1 = mask interrupt. default value is 1 (masked) table 92 power path management interrupts 23.2.10 current sink interrupts the primary cs_int interrupt comprises two sec ondary interrupts as described in section 16.3. the secondary interrupt bits are defined in table 93. each of the secondary interrupts can be masked. when a mask bit is set, the corresponding interrupt event is masked and does not trigger a cs_int in terrupt. the secondary interrupt bits in r16402 (4012h) are valid regardless of w hether the mask bit is set. the se condary interrupts are all masked by default.
WM8310 pre-production w pp, may 2012, rev 3.1 148 address bit label description r16402 (4012h) interrupt status 2 7 cs2_eint current sink 2 interrupt (rising edge triggered) note: cleared when a ?1? is written. 6 cs1_eint current sink 1 interrupt (rising edge triggered) note: cleared when a ?1? is written. r16410 (401ah) interrupt status 2 mask 7 im_cs2_eint interrupt mask. 0 = do not mask interrupt. 1 = mask interrupt. default value is 1 (masked) 6 im_cs1_eint interrupt mask. 0 = do not mask interrupt. 1 = mask interrupt. default value is 1 (masked) table 93 current sink interrupts 23.2.11 real time clock interrupts the primary rtc_int interrupt comprises two sec ondary interrupts as described in section 20.3. the secondary interrupt bits are defined in table 94. each of the secondary interrupts can be masked. when a mask bit is set, the corresponding interrupt event is masked and does not trigger a rtc_int in terrupt. the secondary interrupt bits in r16401 (4011h) are valid regardless of w hether the mask bit is set. the se condary interrupts are all masked by default. address bit label description r16401 (4011h) interrupt status 1 3 rtc_per_eint rtc periodic interrupt (rising edge triggered) note: cleared when a ?1? is written. 2 rtc_alm_eint rtc alarm interrupt (rising edge triggered) note: cleared when a ?1? is written. r16409 (4019h) interrupt status 1 mask 3 im_rtc_per_eint interrupt mask. 0 = do not mask interrupt. 1 = mask interrupt. default value is 1 (masked) 2 im_rtc_alm_eint interrupt mask. 0 = do not mask interrupt. 1 = mask interrupt. default value is 1 (masked) table 94 real time clock (rtc) interrupts 23.2.12 otp memory interrupts the primary otp_int interrupt comprises two sec ondary interrupts as described in section 14.5. the secondary interrupt bits are defined in table 95. each of the secondary interrupts can be masked. when a mask bit is set, the corresponding interrupt event is masked and does not trigger a otp_int in terrupt. the secondary interrupt bits in r16402 (4012h) are valid regardless of w hether the mask bit is set. the se condary interrupts are all masked by default.
pre-production WM8310 w pp, may 2012, rev 3.1 149 address bit label description r16402 (4012h) interrupt status 2 5 otp_cmd_end_eint otp / ice command end interrupt (rising edge triggered) note: cleared when a ?1? is written. 4 otp_err_eint otp / ice command fail interrupt (rising edge triggered) note: cleared when a ?1? is written. r16410 (401ah) interrupt status 2 mask 5 im_otp_cmd_end_eint interrupt mask. 0 = do not mask interrupt. 1 = mask interrupt. default value is 1 (masked) 4 im_otp_err_eint interrupt mask. 0 = do not mask interrupt. 1 = mask interrupt. default value is 1 (masked) table 95 otp memory interrupts 23.2.13 reserved 23.2.14 battery charger interrupts the primary chg_int interrupt comprises six sec ondary interrupts as described in section 17.7.8. the secondary interrupt bits are defined in table 96. each of the secondary interrupts can be masked. when a mask bit is set, the corresponding interrupt event is masked and does not trigger a chg_int in terrupt. the secondary interrupt bits in r16402 (4012h) are valid regardless of w hether the mask bit is set. the se condary interrupts are all masked by default. address bit label description r16402 (4012h) interrupt status 2 15 chg_batt_hot_eint battery hot interrupt (rising edge triggered) note: cleared when a ?1? is written. 14 chg_batt_cold_eint battery cold interrupt (rising edge triggered) note: cleared when a ?1? is written. 13 chg_batt_fail_eint battery fail interrupt (rising edge triggered) note: cleared when a ?1? is written. 12 chg_ov_eint battery overvoltage interrupt (rising edge triggered) note: cleared when a ?1? is written. 11 chg_end_eint battery charge end interrupt (end of charge current threshold reached) (rising edge triggered) note: cleared when a ?1? is written. 10 chg_to_eint battery charge timeout interrupt (charger timer has expired) (rising edge triggered) note: cleared when a ?1? is written. 9 chg_mode_eint battery charge mode interrupt (charger mode has changed) (rising edge triggered) note: cleared when a ?1? is written. 8 chg_start_eint battery charge start interrupt (charging has started)
WM8310 pre-production w pp, may 2012, rev 3.1 150 address bit label description (rising edge triggered) note: cleared when a ?1? is written. r16410 (401ah) interrupt status 2 mask 15 im_chg_batt_hot_eint interrupt mask. 0 = do not mask interrupt. 1 = mask interrupt. default value is 1 (masked) 14 im_chg_batt_cold_ein t interrupt mask. 0 = do not mask interrupt. 1 = mask interrupt. default value is 1 (masked) 13 im_chg_batt_fail_eint interrupt mask. 0 = do not mask interrupt. 1 = mask interrupt. default value is 1 (masked) 12 im_chg_ov_eint interrupt mask. 0 = do not mask interrupt. 1 = mask interrupt. default value is 1 (masked) 11 im_chg_end_eint interrupt mask. 0 = do not mask interrupt. 1 = mask interrupt. default value is 1 (masked) 10 im_chg_to_eint interrupt mask. 0 = do not mask interrupt. 1 = mask interrupt. default value is 1 (masked) 9 im_chg_mode_eint interrupt mask. 0 = do not mask interrupt. 1 = mask interrupt. default value is 1 (masked) 8 im_chg_start_eint interrupt mask. 0 = do not mask interrupt. 1 = mask interrupt. default value is 1 (masked) table 96 battery charger interrupts 23.2.15 high current interrupts the primary hc_int interrupt comprises two secondar y interrupts as described in section 15.13. the secondary interrupt bits are defined in table 97. each of the secondary interrupts can be masked. when a mask bit is set, the corresponding interrupt event is masked and does not trigger a hc_int in terrupt. the secondary interrupt bits in r16404 (4014h) are valid regardless of w hether the mask bit is set. the se condary interrupts are all masked by default.
pre-production WM8310 w pp, may 2012, rev 3.1 151 address bit label description r16404 (4014h) interrupt status 4 9 hc_dc2_eint dc-dc2 high current interrupt (rising edge triggered) note: cleared when a ?1? is written. 8 hc_dc1_eint dc-dc1 high current interrupt (rising edge triggered) note: cleared when a ?1? is written. r16412 (401ch) interrupt status 4 mask 9 im_hc_dc2_eint interrupt mask. 0 = do not mask interrupt. 1 = mask interrupt. default value is 1 (masked) 8 im_hc_dc1_eint interrupt mask. 0 = do not mask interrupt. 1 = mask interrupt. default value is 1 (masked) table 97 overcurrent interrupts 23.2.16 undervoltage interrupts the primary uv_int interrupt comprises f ourteen secondary interrupts as described in section 15.13). the secondary interrupt bits are defined in table 98. each of the secondary interrupts can be masked. when a mask bit is set, the corresponding interrupt event is masked and does not trigger a uv_int in terrupt. the secondary interrupt bits in r16403 (4013h) and r16404 (4014h) are valid regardless of whether the mask bit is set. the secondary interrupts are all masked by default. address bit label description r16403 (4013h) interrupt status 3 9:0 uv_ldo n_eint ldo n undervoltage interrupt (rising edge triggered) note: cleared when a ?1? is written. r16404 (4014h) interrupt status 4 3:0 uv_dcm _eint dc-dc m undervoltage interrupt (rising edge triggered) note: cleared when a ?1? is written. r16411 (401bh) interrupt status 3 mask 9:0 im_uv_ldo n _eint interrupt mask. 0 = do not mask interrupt. 1 = mask interrupt. default value is 1 (masked) r16412 (401ch) interrupt status 4 mask 3:0 im_uv_dc m _eint interrupt mask. 0 = do not mask interrupt. 1 = mask interrupt. default value is 1 (masked) notes: 1. n is a number between 1 and 10 that identifies the individual ldo regulator (ldo1-ldo10). 2. m is a number between 1 and 4 that identifies the individual dc-dc converter (dc1-dc4). table 98 undervoltage interrupts
WM8310 pre-production w pp, may 2012, rev 3.1 152 24 resets and supply voltage monitoring 24.1 resets the WM8310 provides hardware and software monitori ng functions as inputs to a reset management system. these functions enable the device to ta ke appropriate action when power supplies are critically low or if a hardware or software fault condition is detected. there are different levels of resets, providi ng different response mechanisms according to the condition that caused the reset ev ent. where applicable, the WM8310 will automatically return to the on state and resume normal operation as quickly as possible following a reset. a system reset occurs in the event of a power sequence failure, device overtemperature, sysvdd undervoltage, software ?off? request or vpmic (ldo12) undervoltage condition. under these conditions, the WM8310 asserts the reset pin and transitions to the off state. in the case of vpmic undervoltage, the WM8310 enters the backup stat e. the contents of the register map are not reset under system reset conditions. a device reset occurs in the event of a watc hdog timeout, hardware reset request or converter (ldo or dc-dc) undervoltage condition. under these conditions, the WM8310 asserts the reset pin and transitions to the off state. the contents of the register map are cleared to default values, except for the rtc and software scratch regi sters, which are maintained. the WM8310 will automatically return to the on state after performing the device reset. a software reset occurs when any value is written to register 0000h, as described in section 12.5. in this event, the WM8310 asserts the reset pin and transitions to the off state. the register map contents may or may not be affected, depending on the value of the sw_reset_cfg field. see section 24.3 for further details of software reset configuration. the WM8310 will automatically return to the on state after performing the software reset. a power-on reset occurs when the supply voltage is less than the power-on reset threshold, as described in section 24.4. in this event, the WM8310 is forced into the no power state, as described in section 11.2. all the contents of the register map are lost in the no power state.
pre-production WM8310 w pp, may 2012, rev 3.1 153 a summary of the WM8310 resets is contained in table 99. reset type reset condition description response automatic recovery system reset power sequence failure dc converters, ldos or clkout circuits (includi ng fll) have failed to start up within the permitted time. see section 11.3. assert reset pin. select off state. if the reset condition is vpmic (ldo12) undervoltage, then the WM8310 enters the backup state. no device overtemperature an overtemperature condition has been detected. see section 26. no sysvdd undervoltage (1) sysvdd is less than the user- selectable threshold syslo_thr and syslo_err_act is configured to select off in this condition. see section 24.4. no sysvdd undervoltage (2) sysvdd is less than the shutdown voltage. see section 24.4. no software off request off has been commanded by writing chip_on = 0. see section 11.3 no vpmic (ldo12) undervoltage the WM8310 supply voltage is less than the system reset threshold. see section 24.4. no device reset watchdog timeout wa tchdog timer has expired and the selected response is to generate a device reset. see section 25. assert reset pin. shutdown and restart the WM8310. reset register map (note the rtc and software scratch registers are not reset.) yes hardware reset the reset pin has been pulled low by an external source. see section 24.2. yes converter (ldo or dc- dc) undervoltage an undervoltage condition has been detected and the selected response is ?shut down system (device reset)? see section 15. yes software reset software reset software reset has been commanded by writing to register 0000h. see section 12.5. assert reset pin. shutdown and restart the WM8310. see section 24.3 for configurable options regarding the register map contents. yes power on reset power on reset the WM8310 supply voltage is less than the power-on reset (por) threshold. see section 24.4. the WM8310 is in the no power state. all register contents are lost. no table 99 resets summary in the cases where automatic recovery is suppor ted (as noted in table 99), the WM8310 will re-start the WM8310 following the reset, and return the device to the on state. the particular reset condition which caused the return to the on state w ill be indicated in the ?on source? register - see section 11.3. note that, if a watchdog timeout or converter under voltage fault persists, a maximum of 6 device resets will be attempted to initiate the start-up sequence. similarly, a maximum of 6 software resets is permitted. if these limits are exceeded, the WM8310 will remain in the off state until the next valid on state transition event occurs.
WM8310 pre-production w pp, may 2012, rev 3.1 154 the WM8310 asserts the reset low as soon as the device begins the shutdown sequence. reset is held low for the duration of the shutdown sequence and is held low in the off state. in the cases where automatic recovery is supported, reset is automatically cleared (high) after successful completion of the startup sequence. the duration of the reset low period after the startup sequence has completed is governed by the rst_dur r egister field described in section 11.7. 24.2 hardware reset a hardware reset is triggered when an external source pulls the reset pin low. under this condition, the WM8310 transitions to the off state. the contents of the register map are cleared to default values, except for the rtc and software scr atch registers, which are maintained. the WM8310 will then automatically schedule an on state transition to resume normal operation. if the external source continues to pull the reset pin low, then the wm 8310 cannot fully complete the on state transition following the hardware reset. in this case, the WM8310 will mask the external reset for up to 32 seconds. if the reset pin is released (ie. it returns to logic ?1?) during this time, then the on state transition is completed and the hard ware reset input is valid again from this point. if the reset pin is not releas ed, then the WM8310 will force an off condition on expiry of the 32 seconds timeout. recovery from this forced o ff condition cannot occur until the external reset condition is de-asserted, followed by a valid on event. if an on event occurs before the external reset is de-asserted, then start-up will be attempted, but the transition will be unsuccessful, causing a return to the off state. it is possible to mask the reset pin input in the sl eep state by setting the rst_slp_msk register bit as described in section 11.7. 24.3 software reset a software reset is triggered by writing to register 0000h, as described in section 12.5. in this event, the WM8310 asserts the reset pin and transitions to the off state. if the reset occurred in the on state, then the WM8310 will automatically return to the on state following the reset. the swrst_dly register field determines whether a time delay is applied between the software reset command and the resultant shutdown and st art-up sequences. when t he swrst_dly bit is set, the programmable time delay pwrstate_d ly is applied before commencing the shutdown sequence. the timing of the software reset is illustrated in figure 30. see section 11.3 for a definition of the pwrstate_dly register. the sw_reset_cfg register field determines if t he register map is reset under a software reset condition. note that the sw_reset_cfg control register is locked by the WM8310 user key. this register can only be changed by writing the appropriate code to the se curity register, as described in section 12.4. address bit label default description r16387 (4003h) power state 9 swrst_dly 0 software reset delay 0 = no delay 1 = software reset is delayed by pwrstate_dly following the software reset command r16390 (4006h) reset control 10 sw_reset_c fg 1 software reset configuration. selects whether the register map is reset to default values when software reset occurs. 0 = all registers except rtc and software scratch registers are reset by software reset 1 = register map is not affected by software reset protected by user key table 100 software reset configuration
pre-production WM8310 w pp, may 2012, rev 3.1 155 the timing details of the software reset are illustrated in figure 30. sw reset command on transition completes reset is de-asserted power state time reset pin on transition starts on on software reset (shutdown / start-up) time delay set by swrst_dly and pwrstate_delay 0ms, 1ms or 10ms off transition then on transition nominal duration = 10 x 2ms reset delay set by rst_dur 3ms, 11ms, 51ms or 101ms figure 30 software reset timing
WM8310 pre-production w pp, may 2012, rev 3.1 156 24.4 supply voltage monitoring the WM8310 includes a number of mechanisms to prevent the system from starting up, or to force it to shut down, when the power sources are critically low. the power supply configuration for the WM8310 is de scribed in section 17. the chip automatically chooses the most suitable supply, selecting bet ween a wall adapter supply, usb or battery. the preferred source is routed to the sysvdd pin, to which the other power management circuits would typically be connected. the sysvdd voltage is monitored internally, as described below. the internal regulator ldo12 is powered from an internal domain equivalent to sysvdd and generates an internal supply (vpmic) to support vari ous ?always-on? functions. in the absence of the wall, usb or battery supplies, ldo12 can be power ed from a backup supply. (note that sysvdd is not maintained by the backup supply.) the vpmic monitoring function controls the power-on reset circuit, which sets the threshold below which the WM8310 cannot operate. the operation of the vpmic monitoring circuit is illu strated in figure 31. the internal signal porrst is governed by the v por thresholds. these determine when t he WM8310 is kept in the no power state. the internal signal pmicrst is gover ned by the v res thresholds. these determine when the WM8310 is kept in the backup state. the vpmic monitoring thresholds illustrated in figur e 31 are fixed. the voltage levels are defined in the electrical characteri stics - see section 7.5. backup no power backup no power figure 31 vpmic monitoring the operation of the sysvdd monitoring circ uit is illustrated in figure 32. the v shutdown threshold is the voltage below which the WM8310 forces an off trans ition. this threshold voltage is fixed and is defined in the electrical charac teristics - see section 7.5. the v sysok threshold is the level at which the internal signal sysok is asserted. any on request will be inhibited if sysok is not set. the v sysok threshold can be set using t he sysok_thr register field in accordance with the minimum voltage requirement s of the application. note that a hysteresis margin is added to the sysok_thr setting; see section 7.5 for details. the v syslo threshold is the level at which the internal signal syslo is asserted. this indicates a sysvdd undervoltage condition, at which a sele ctable response can be initiated. the v syslo threshold can be set using the syslo_thr regist er field. the action taken under this undervoltage condition is selected using the syslo_err_act regist er field, as defined in table 101. an interrupt event is associated with the sy slo condition - see section 17.5.
pre-production WM8310 w pp, may 2012, rev 3.1 157 the syslo status can be read from the syslo_sts register bit. this bit is asserted when sysvdd is below the syslo threshold. the WM8310 can also indicate the status of t he sysok signal via a gpio pin configured as a ?sysvdd good? output (see section 21). a gpio pin configured as ?sysvdd good? output will be asserted when the sysvdd is above the sysok threshold. v sysok v sysvdd time v syslo v shutdown sysok (syslo) shutdown time time figure 32 sysvdd monitoring address bit label default description r16385 (4001h) sysvdd control 15:14 syslo_err_ act 00 syslo error action selects the action taken when syslo is asserted 00 = interrupt 01 = wake transition 10 = reserved 11 = off transition 11 syslo_sts 0 syslo status 0 = normal 1 = sysvdd is below syslo threshold 6:4 syslo_thr [2:0] 010 syslo threshold (falling sysvdd) this is the falling sysvdd voltage at which syslo will be asserted 000 = 2.8v 001 = 2.9v ? 111 = 3.5v 2:0 sysok_thr [2:0] 101 sysok threshold (rising sysvdd) this is the rising sysvdd voltage at which sysok will be asserted 000 = 2.8v 001 = 2.9v ? 111 = 3.5v note that the sysok hysteresis margin is added to these threshold levels. table 101 sysvdd monitoring control
WM8310 pre-production w pp, may 2012, rev 3.1 158 25 watchdog timer the WM8310 includes a watchdog timer designed to detect a possible software fault condition where the host processor has locked up. the watc hdog timer is a free-running counter driven by the internal rc oscillator. the watchdog timer is enabled by default; it c an be enabled or disabled by writing to the wdog_ena register bit. the watchdog behaviour in sl eep is configurable; it can either be set to continue as normal or to be disabled. the watchdog behaviour in sleep is determined by the wdog_slpena bit. the watchdog timer duration is set using wd og_to. the watchdog timer can be halted for debug purposes using the wdog_debug bit. the watchdog reset source is selectable between software and hardware triggers. (note that the de- selected reset source has no effect.) if the watc hdog is not reset within a programmable timeout period, this is interpreted by the WM8310 as a fault condition. the wa tchdog timer then either triggers a device reset, or issues a wake reques t or raises an interrupt. the action taken is determined by the wdog_primact register field. if the watchdog is not reset within a further timeout period of the watchdog counter, a secondary action is triggered. the secondar y action taken at this point is determined by the wdog_secact register field. the watchdog reset source is selected using the wdog_rst_src register bit. when software wdog reset source is selected, the watchdog is reset by writing a ?1? to the wdog_reset field. when hardware wdog reset source is selected, t he watchdog is reset by toggling a gpio pin that has been configured as a watchdog reset input (see section 21). if a device reset is triggered by the watchdog timeout, the WM8310 asserts the reset pin, resets the internal control registers (excluding the rtc) and initiates a start-up sequence. the watchdog timer is not automatically reset as part of the device reset; the watchdog must be reset by the host application following the device reset. note that, following a device reset, the action taken on subsequent timeout of the watchdog timer will be determined by the wdog_primact register. if the watchdog timeout fault persists, then a maximum of 6 device reset attempts will be made. see section 24. if the watchdog timeout occurs more than 6 times, the WM8310 will remain in the off state until the next valid on state transition event occurs. note that the watchdog control registers are lock ed by the WM8310 user key. these registers can only be changed by writing the appropriate code to the se curity register, as described in section 12.4. address bit label default description r16388 (4004h) watchdog 15 wdog_ena 1 watchdog timer enable 0 = disabled 1 = enabled (enables the watchdog; does not reset it) protected by user key 14 wdog_debu g 0 watchdog pause 0 = disabled 1 = enabled (halts the watchdog timer for system debugging) protected by user key 13 wdog_rst_s rc 1 watchdog reset source 0 = hardware only 1 = software only protected by user key 12 wdog_slpe na 0 watchdog sleep enable 0 = disabled 1 = controlled by wdog_ena protected by user key
pre-production WM8310 w pp, may 2012, rev 3.1 159 address bit label default description 11 wdog_rese t 0 watchdog software reset 0 = normal 1 = watchdog reset (resets the watchdog, if wdog_rst_src = 1) protected by user key 9:8 wdog_seca ct 10 secondary action of watchdog timeout (taken after 2 timeout periods) 00 = no action 01 = interrupt 10 = device reset 11 = wake transition protected by user key 5:4 wdog_prima ct 01 primary action of watchdog timeout 00 = no action 01 = interrupt 10 = device reset 11 = wake transition protected by user key 2:0 wdog_to [2:0] 111 watchdog timeout period 000 = 0.256s 001 = 0.512s 010 = 1.024s 011 = 2.048s 100 = 4.096s 101 = 8.192s 110 = 16.384s 111 = 32.768s protected by user key table 102 controlling the watchdog timer the watchdog timeout interrupt event is indicat ed by the wdog_to_eint register field. this secondary interrupt triggers a primary watchdog in terrupt, wdog_int (see section 23). this can be masked by setting the mask bit as described in table 103. address bit label description r16401 (4011h) interrupt status 1 11 wdog_to_eint watchdog timeout interrupt. (rising edge triggered) note: cleared when a ?1? is written. r16409 (4019h) interrupt status 1 mask 11 im_wdog_to_eint interrupt mask. 0 = do not mask interrupt. 1 = mask interrupt. default value is 1 (masked) table 103 watchdog timer interrupts
WM8310 pre-production w pp, may 2012, rev 3.1 160 26 temperature sensing the WM8310 provides temperature moni toring as status information and also for self-protection of the device. temperature monitoring is al ways enabled in the on and sleep states. the thermal warning temperature can be set usi ng the thw_temp register field. the thermal warning hysteresis ensures that the thw_temp is not reset until the device temperature has dropped below the threshold by a suitable margin. the extent of the hysteresis can be selected using the thw_hyst register field. the thermal warning condition c an be read using the thw_sts regi ster bit. an overtemperature condition causes the thermal warning interrupt (temp_thw_cint) to be set. the thermal warning interrupt is also set when the overtemperature condi tion clears, ie. when the device has returned to its normal operating limits. the thermal shutdown temperature is set at a fix ed level. if a thermal shutdown condition is detected whilst in the on or sleep states, then a system re set is triggered, as described in section 24.1, forcing a transition to the off state. the temperature sensing circuit is configured and monitored using t he register fields described in table 104. address bit label default description r16386 (4002h) 3 thw_hyst 1 thermal warning hysteresis 0 = 8 degrees c 1 = 16 degrees c 1:0 thw_temp [1:0] 10 thermal warning temperature 00 = 90 degrees c 01 = 100 degrees c 10 = 110 degrees c 11 = 120 degrees c r16397 (400dh) 15 thw_sts 0 thermal warning status 0 = normal 1 = overtemperature warning (warning temperature is set by thw_temp) table 104 temperature sensing control the thermal warning interrupt event is indicat ed by the temp_thw_cint register field. this secondary interrupt triggers a prim ary thermal interrupt, temp_int (see section 23). this can be masked by setting the mask bit as described in table 105. address bit label description r16401 (4011h) interrupt status 1 1 temp_thw_cint thermal warning interrupt (rising and falling edge triggered) note: cleared when a ?1? is written. r16410 (4019h) interrupt status 1 mask 1 im_temp_thw_cint interrupt mask. 0 = do not mask interrupt. 1 = mask interrupt. default value is 1 (masked) table 105 thermal interrupts
pre-production WM8310 w pp, may 2012, rev 3.1 161 27 voltage and current references 27.1 voltage reference (vref) the main voltage reference generated by the WM8310 is bonded to the vrefc pin. the accuracy of this reference is optimised by factory-set trim registers. the voltage reference (vref) requires an external decoupling capacitor; a 100nf x5r capacitor is recommended for typical applications, as noted in section 30.2. if usb100ma_startup=1x (see section 17.4), then a 50nf capacitor should be used. omitting this capacitor will result in increased noise on the voltage reference; this will particularly affect the analogue ldos. the vrefc capacitor should be grounded to the refgnd pin. the voltage reference circuit includes a low-power mode, which enables power consumption to be minimised where appropriate. the low-power refe rence mode may lead to increased noise on the voltage reference; this mode should only be sele cted when minimum power consumption is more important than voltage stability. note that the low power reference mode is not supported when the auxiliary adc function is enabled. the low power reference mode is enabled when ref_lp register is set. the low power reference mode should only be enabled when the auxiliary adc is disabled. enabling the low power reference mode will lead to a malfunction of the auxiliary adc function. address bit label default description r16387 (4003h) 12 ref_lp 0 low power voltage reference control 0 = normal 1 = low power reference mode select note that low power reference mode is only supported when the auxiliary adc is disabled. table 106 low power voltage reference control 27.2 current reference (iref) the power management circuits of the wm 8310 use an integrated current reference. this current reference (iref) requires the connecti on of an external resistor to the irefr pin; a 100k ? (1%) resistor is recommended, as noted in se ction 30.2. the WM8310 will malfunction if this resistor is omitted. the irefr resistor should be grounded to the refgnd pin.
WM8310 pre-production w pp, may 2012, rev 3.1 162 28 register map overview de c ad d r he x ad d r nam e 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bin default 0 0000 res et id 0000_0000_0000_0000 1 0001 revision 0000_0000_0000_0000 2 0002 res er v ed 0000000000000000 0000_0000_0000_0000 3 0003 res er v ed 0000000000000000 0000_0000_0000_0000 4 0004 res er v ed 0000000000000000 0000_0000_0000_0000 5 0005 res er v ed 0000000000000000 0000_0000_0000_0000 6 0006 res er v ed 0000000000000000 0000_0000_0000_0000 7 0007 res er v ed 0000000000000000 0000_0000_0000_0000 16384 4000 parent id 0110_0010_0000_0100 16385 4001 sy sv dd contr ol 00 syslo_sts 0000 0 0000_0000_0010_0101 16386 4002 thermal monitoring 000000000000 thw_hy st 0 0000_0000_0000_1010 16387 4003 po w e r st a t e chip_on chip_slp 0 ref_lp swrst_dl y 000 usb_curr_ sts uu00_1000_0000_0010 16388 4004 watchdog wdog_ena wdog_deb ug wdog_rst _src wdog_slp ena wdog_res et 0000 1010_p010_0001_0111 16389 4005 on pin control 000000 00 on_pin_sts 0 0000_0001_0000_0000 16390 4006 res et contr ol reconfig_ at_on 0 wall_fet_ ena_drv_s tr batt_fet_ ena 0 sw_ reset_ cfg 000 auxrst_sl pena rst_slp_m sk rst_ sl pen a 00 1000_0100_0111_0011 16391 4007 control interface 0000000000000 autoinc 00 0000_0000_0000_0100 16392 4008 security key 0000_0000_0000_0000 16393 4009 sof tw are scratch 0000_0000_0000_0000 16394 400a otp control otp_ prog 0 otp_mem 0 otp_fina l otp_v erif y otp_ write otp_ rea d otp_ bul k 000 u010_0000_0000_0000 16395 400b security key 2 0000000000000000 0000_0000_0000_0000 16396 400c gpio level 0000 gp12_lvl gp11_lvl gp10_lvl gp9_lvl gp8_lvl gp7_lvl gp6_lvl gp5_lvl gp4_lvl gp3_lvl gp2_lvl gp1_lvl 0000_0000_0000_0000 16397 400d system status thw_sts 0000 pwr_ src_ batt pwr_wa ll pwr_usb 000 0000_0000_0000_0000 16398 400e on source on_tra ns 000 on_gpio on_syslo 0 on_chg on_wdog_ to on_sw_re q on_rtc_al m on_on_pin reset_cnv _uv reset_sw reset_hw reset_wd og 0000_0000_0000_0000 16399 400f off sourc e 00 off_intldo _err off_pwr_s eq off_gpio off_sysv dd off_therr 00 off_sw_re q 0 off_on_pin 0000 0000_0000_0000_0000 16400 4010 system interrupts ps_int temp_int gp_int on_pin_int wdog_int 00 auxadc_in t ppm_int cs_int rtc_int otp_int 0 chg_ int hc_ int uv _ int pppp_ pppp_ pppp_ pppp 16401 4011 interrupt status 1 ppm_syslo _eint ppm_ pwr_ s rc_eint ppm_ usb_ c urr_eint on_pin_cin t wdog_to_ eint 00 auxadc_d ata_eint auxadc_d comp4_eint a uxa dc_d comp3_eint auxadc_d comp2_eint auxadc_d comp1_eint rtc_per_ei nt rtc_a lm_ei nt temp_thw_ cint 0 pppp_ pppp_ pppp_ ppp0 16402 4012 interrupt status 2 chg_ba tt_ hot_eint chg_ba tt_ cold_eint chg_ba tt_ fa il_eint chg_ov _ei nt chg_ end_ ei nt chg_to_ei nt chg_mode _eint chg_sta rt _eint cs2_eint cs1_eint otp_cmd_e nd_eint otp_ err_ ei nt 0 ps_por_ein t ps_ sl eep_ off_eint ps_ on_ wa ke_eint pppp_ pppp_ pppp_ 0 ppp 16403 4013 interrupt status 3 000000 uv_ldo10_ eint uv_ldo9_ei nt uv_ldo8_ei nt uv_ldo7_ei nt uv_ldo6_ei nt uv_ldo5_ei nt uv_ldo4_ei nt uv_ldo3_ei nt uv_ldo2_ei nt uv_ldo1_ei nt 0000_00pp_ pppp_ pppp 16404 4014 interrupt status 4 000000 hc_dc2_ein t hc_dc1_ein t 0000 uv_dc4_ein t uv_dc3_ein t uv_dc2_ein t u v_dc1_ein t 0000_00pp_pp00_ pppp 16405 4015 interrupt status 5 0000 gp12_eint gp11_eint gp10_eint gp9_eint gp8_eint gp7_eint gp6_eint gp5_eint gp4_eint gp3_eint gp2_eint gp1_eint pppp_ pppp_ pppp_ pppp 16406 4016 res er v ed 0000000000000000 0000_0000_0000_0000 16407 4017 irq conf ig 00000000000000 irq_od im_irq 0000_0000_0000_0010 ma in_sta te[4:0] on_pin_secact[1:0] on_pin_primact[1:0] on_pin_to[1:0] rst_dur[1:0] security[15:0] sw_scratch[15:0] otp_read_lvl[1:0] otp_ pa ge[ 1 : 0 ] sysok_thr[2:0] thw_temp[1:0] pwrstate_dly[1:0] usb100ma_startup[1:0] usb_ilim[2:0] wdog_secact[1:0] wdog_prima ct[1:0] wdog_to[2:0] chip_id[15:0] pa rent_ rev [ 7 : 0 ] child_rev [7:0] parent_id[15:0] sy slo_err_act[1:0] syslo_thr[2:0]
pre-production WM8310 w pp, may 2012, rev 3.1 163 dec addr hex addr nam e 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bin default 16408 4018 system interrupts mask im_ps_int im_temp_in t im_gp_int im_on_pin_ int im_wdog_i nt 11 im_a uxa d c_int im_ppm_int im_cs_int im_rtc_int im_otp_int 1 im_chg_in t im_hc_int im_uv_int 1111_1111_1111_1111 16409 4019 interrupt status 1 mask im_ppm_sy slo_eint im_ppm_pw r_src_ein t im_ppm_us b_curr_ei nt im_on_pin_ cint im_wdog_ to_eint 11 im_a uxa d c_da ta _ei nt im_a uxa d c_dcomp4 eint im_a uxa d c_dcomp3 eint im_a uxa d c_dcomp2 eint im_a uxa d c_dcomp1 eint im_rtc_pe r_eint im_rtc_a l m_eint im_temp_ t hw_cint 0 1111_1111_1111_1110 16410 401a interrupt status 2 mask im_chg_ba tt_hot_ein t im_chg_ba tt_cold_e int im_chg_ba tt_fa il_ei nt im_chg_o v_eint im_chg_en d_eint im_chg_to _eint im_chg_m ode_eint im_chg_st art_eint im_cs2_ein t im_cs1_ein t im_otp_cm d_end_ein t im_otp_er r_eint 0 im_ps_por _eint im_ps_sle ep_ off_ ein t im_ps_on_ wake_eint 1111_1111_1111_0111 16411 401b interrupt status 3 mask 000000 im_uv_ldo 10_eint im_uv_ldo 9_eint im_uv_ldo 8_eint im_uv _ldo 7_eint im_uv_ldo 6_eint im_uv _ldo 5_eint im_uv _ldo 4_eint im_uv_ld o3_eint im_uv_ldo 2_eint im_uv_ldo 1_eint 0000_0011_1111_1111 16412 401c interrupt status 4 mask 000000 im_hc_dc2 _eint im_hc_dc1 _eint 1000 im_uv _dc4 _eint im_uv _dc 3_eint im_uv _dc2 _eint im_uv _dc1 _eint 0000_0011_1000_1111 16413 401d interrupt status 5 mask 1111 im_gp12_ei nt im_gp11_ei nt im_gp10_ei nt im_gp9_ein t im_gp8_ein t im_gp7_ein t im_gp6_ein t im_gp5_ein t im_gp4_ein t im_gp3_ei nt im_gp2_ein t im_gp1_ein t 1111_1111_1111_1111 16414 401e res er v ed 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0000_0000_0000_0000 16415 401f res er v ed 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0000_0000_0000_0000 16416 4020 rtc write counter 0000_0000_0000_0000 16417 4021 rtc time 1 0000_0000_0000_0000 16418 4022 rtc time 2 0000_0000_0000_0000 16419 4023 rtc a lar m 1 0000_0000_0000_0000 16420 4024 rtc a lar m 2 0000_0000_0000_0000 16421 4025 rtc contr ol rtc_v a lid rtc_sy nc _busy 00 0 rtc_a lm_ ena 0 0 0 0 0 0 0 0000_0000_0000_0000 16422 4026 rtc tr im 000000 0000_0000_0000_0000 16423 4027 res er v ed 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0000_0000_0000_0000 16424 4028 touch control 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0u00_0000_0100_0000 16425 4029 touch control 2 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0000_0000_0000_0111 16426 402a touch data x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0000_0000_0000_0000 16427 402b touc h data y 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0000_0000_0000_0000 16428 402c touch data z 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0000_0000_0000_0000 16429 402d auxadc data 0000_0000_0000_0000 16430 402e a ux a dc contr ol aux_ena aux_cvt_ ena 0 aux_slpe na 000000 0u00_0000_0000_0000 16431 402f auxadc source 000000 aux_wall _sel aux_batt _sel aux_usb_ sel aux_sysv dd_sel aux_batt _temp_sel a ux_chip_ temp_sel aux_aux4 _sel aux_aux3 _sel aux_aux2 _sel aux_aux1 _sel 0000_0000_0000_0000 16432 4030 comparator control 0000 dcomp4_s ts dcomp3_s ts dcomp2_s ts dcomp1_s ts 0000 dcmp4_en a dcmp3_en a dcmp2_en a dcmp1_en a 0000_0000_0000_0000 16433 4031 comparator 1 dcmp1_gt 0000_0000_0000_0000 16434 4032 comparator 2 dcmp2_gt 0000_0000_0000_0000 16435 4033 comparator 3 dcmp3_gt 0000_0000_0000_0000 16436 4034 comparator 4 dcmp4_gt 0000_0000_0000_0000 16437 4035 res er v ed 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0000_0000_0000_0000 16438 4036 re s er v ed 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0000_0000_0000_0000 16439 4037 res er v ed 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0000_0000_0000_0000 dcmp4_thr[11:0] aux_rate[5:0] dcmp1_src[2:0] dcmp1_thr[11:0] dcmp2_src[2:0] dcmp2_thr[11:0] dcmp3_src[2:0] dcmp3_thr[11:0] dcmp4_src[2:0] a ux_da ta _src[3:0] aux_data[11:0] rtc_wr_cnt[15:0] rtc_time[31:16] rtc_time[15:0] rtc_a lm[31:16] rtc_a lm[15:0] rtc_pint_freq[2:0] rtc_trim[9:0]
WM8310 pre-production w pp, may 2012, rev 3.1 164 dec addr hex addr nam e 1514131211109876543210 bin default 16440 4038 gpio1 control gp1_dir gp1_int_m ode gp1_pwr_ dom gp1 _ pol gp1 _ od 0 gp1 _ ena 0 0 0 1010_0100_0000_0000 16441 4039 gpio2 control gp2_dir gp2_int_m ode gp2_pwr_ dom gp2 _ pol gp2 _ od 0 gp2 _ ena 0 0 0 1010_0100_0000_0000 16442 403a gpio3 control gp3_dir gp3_int_m ode gp3_pwr_ dom gp3 _ pol gp3 _ od 0 gp3 _ ena 0 0 0 1010_0100_0000_0000 16443 403b gpio4 control gp4_dir gp4_int_m ode gp4_pwr_ dom gp4 _ pol gp4 _ od 0 gp4 _ ena 0 0 0 1010_0100_0000_0000 16444 403c gpio5 control gp5_dir gp5_int_m ode gp5_pwr_ dom gp5 _ pol gp5 _ od 0 gp5 _ ena 0 0 0 1010_0100_0000_0000 16445 403d gpio6 control gp6_dir gp6_int_m ode gp6_pwr_ dom gp6 _ pol gp6 _ od 0 gp6 _ ena 0 0 0 1010_0100_0000_0000 16446 403e gpio7 control gp7_dir gp7_int_m ode gp7_pwr_ dom gp7 _ pol gp7 _ od 0 gp7 _ ena 0 0 0 1010_0100_0000_0000 16447 403f gpio8 control gp8_dir gp8_int_m ode gp8_pwr_ dom gp8 _ pol gp8 _ od 0 gp8 _ ena 0 0 0 1010_0100_0000_0000 16448 4040 gpio9 control gp9_dir gp9_int_m ode gp9_pwr_ dom gp9_pol gp9_od 0 gp9_ena 0 0 0 1010_0100_0000_0000 16449 4041 gpio10 control gp10_dir gp10_int_ mode gp10_pwr _dom gp10_pol gp10_od 0 gp10_ena 0 0 0 1010_0100_0000_0000 16450 4042 gpio11 control gp11_dir g p11_int_ mode gp11_pwr _dom gp11_pol gp11_od 0 gp11_ena 0 0 0 1010_0100_0000_0000 16451 4043 gpio12 control gp12_dir gp12_int_ mode gp12_pwr _dom gp12_pol gp12_od 0 gp12_ena 0 0 0 1010_0100_0000_0000 16452 4044 gpio13 control 101001000000 00001 0 1 0 _ 0 1 0 0 _ 0 0 0 0 _ 0 0 0 0 16453 4045 gpio14 control 101001000000 00001 0 1 0 _ 0 1 0 0 _ 0 0 0 0 _ 0 0 0 0 16454 4046 gpio15 control 101001000000 00001 0 1 0 _ 0 1 0 0 _ 0 0 0 0 _ 0 0 0 0 16455 4047 gpio16 control 101001000000 00001 0 1 0 _ 0 1 0 0 _ 0 0 0 0 _ 0 0 0 0 16456 4048 charger control 1 c h g _ e n ac h g _ f r c0 0000c h g _ f a s t000 chg_imon_ ena chg_chip_ temp_mon 0000_0000_0000_0001 16457 4049 charger control 2 0 chg_off_ msk 00 0000_0110_0000_0010 16458 404a charger status batt_ov_s ts batt_hot _sts batt_col d_sts chg_topo ff chg_a ctiv e 0000_0000_0000_0000 16459 404b res er v ed 00000000000000000 0 0 0 _ 0 0 0 0 _ 0 0 0 0 _ 0 0 0 0 16460 404c status led 1 0000 00 1100_0000_0010_0110 16461 404d status led 2 0000 00 1100_0000_0010_0110 16462 404e current sink 1 cs1_ena cs1_driv e cs1_sts cs1_slpen a 00 0u00_0101_0000_0000 16463 404f current sink 2 cs2_ena cs2_driv e cs2_sts cs2_slpen a 00 0u00_0101_0000_0000 16464 4050 dcdc enable 00000000e p e 2 _ e n ae p e 1 _ e n a00d c 4 _ e n ad c 3 _ e n ad c 2 _ e n ad c 1 _ e n a0 0 0 0 _ 0 0 0 0 _ u u 0 0 _ uuuu 16465 4051 ldo enable 00000 ldo11_en a ldo10_en a ldo9_ena ldo8_ena ldo7_ena ldo6_ena ldo5_ena ldo4_ena ldo3_ena ldo2_ena ldo1_ena 0000_0uuu_uuuu_uuuu 16466 4052 dcdc status 00000000e p e 2 _ s t se p e 1 _ s t s00d c 4 _ s t sd c 3 _ s t sd c 2 _ s t sd c 1 _ s t s0 0 0 0 _ 0 0 0 0 _ 0 0 0 0 _ 0 0 0 0 16467 4053 ldo status 0 0 0 0 0 ldo11_sts ldo10_sts ldo9_sts ldo8_sts ldo7_sts ldo6_sts ldo5_sts ldo4_sts ldo3_sts ldo2_sts ldo1_sts 0000_0000_0000_0000 16468 4054 dcdc uv status 00 dc2_ov _s ts dc1_ov _s ts 00 dc2_hc_st s dc1_hc_st s 0000 dc4_uv _st s dc3_uv _s ts dc2_uv_s ts dc1_uv_s ts 0000_0000_0000_0000 16469 4055 ldo uv status intldo_uv _sts 00000 ldo10_uv _sts ldo9_uv_ sts ldo8_uv_ sts ldo7_uv_ sts ldo6_uv_ sts ldo5_uv_ sts ldo4_uv_ sts ldo3_uv_ sts ldo2_uv_ sts ldo1_uv_ sts 0000_0000_0000_0000 16470 4056 dc1 contr ol 1 0 dc1_pha s e 0 0 dc1_flt 0 0 0 1000_0000_0000_0000 16471 4057 dc1 contr ol 2 0 dc1_hwc_ vsel 00 0 0 dc1_hc_in d_ena 0000_0011_0000_0000 dc1_hwc_src[1:0] dc1_hwc_mode[1:0] dc1_hc_thr[2:0] cs2_off_ra mp[1:0] cs2_on_ramp[1:0] cs2_isel[5:0] dc1_ra te[1:0] dc1_freq[1:0] dc1_soft_start[1:0] dc1_cap[1:0] dc1_err_act[1:0] led2_src[1:0] led2_mode[1:0] led2_seq_len[1:0] led2_dur[1:0] led2_duty _cy c[1:0] cs1_off_ra mp[1:0] cs1_on_ramp[1:0] cs1_isel[5:0] chg_fast_ilim[3:0] chg_state[2:0] chg_time_ela psed[7:0] led1_src[1:0] led1_mode[1:0] led1_seq_len[1:0] led1_dur[1:0] led1_duty _cy c[1:0] chg_iterm[2:0] chg_time[3:0] chg_trkl_ilim[1:0] chg_vsel[1:0] gp12_pull[1:0] gp12_fn[3:0] gp8_pull[1:0] gp8_fn[3:0] gp9_pull[1:0] gp9_fn[3:0] gp10_pull[1:0] gp10_fn[3:0] gp11_pull[1:0] gp11_fn[3:0] gp4_fn[3:0] gp5_pull[1:0] gp5_fn[3:0] gp6_pull[1:0] gp6_fn[3:0] gp7_pull[1:0] gp7_fn[3:0] gp1_pull[1:0] gp1_fn[3:0] gp2_pull[1:0] gp2_fn[3:0] gp3_pull[1:0] gp3_fn[3:0] gp4_pull[1:0]
pre-production WM8310 w pp, may 2012, rev 3.1 165 de c ad dr he x a dd r nam e 1514131211109876543210 bin default 16472 4058 dc1 on conf ig 000 0 0000_0001_0000_0000 16473 4059 dc1 sleep contr ol 000 0 0000_0011_0000_0000 16474 405a dc1 dv s contr ol 000 0000 0000_0000_0000_0000 16475 405b dc2 contr ol 1 0 dc2_pha se 00 dc2_flt 000 1001_0000_0000_0000 16476 405c dc2 contr ol 2 0 dc2_hwc_ vsel 0 000 dc2_hc_ind _ena 0000_0011_0000_0000 16477 405d dc2 on conf ig 000 0 0000_0001_0000_0000 16478 405e dc2 sleep contr ol 000 0 0000_0011_0000_0000 16479 405f dc2 dv s contr ol 000 0000 0000_0000_0000_0000 16480 4060 dc3 contr ol 1 000 dc3_pha se 0000 dc3_flt 0 0000_0000_0001_0100 16481 4061 dc3 contr ol 2 0 dc3_hwc_ vsel dc3_ovp 0000000 0000_0011_0000_0000 16482 4062 dc3 on conf ig 000 0 0000_0001_0000_0000 16483 4063 dc3 sleep contr ol 000 0 0000_0011_0000_0000 16484 4064 dc4 contr ol 000 dc4_hwc_ mode 0000 0 dc4_fbsrc 0000_0001_0000_0100 16485 4065 dc4 sleep contr ol 0000000 dc4_slpen a 00000000 0000_0000_0000_0000 16486 4066 epe1 co n t r o l 00 epe1 _ hwce na 00000 0000_0000_0000_0000 16487 4067 epe2 co n t r o l 00 epe2 _ hwce na 00000 0000_0000_0000_0000 16488 4068 ldo1 control 0 ldo1_hwc _vsel ldo1_flt ldo1_swi 00000 l do1_lp_m ode 0000_0010_0000_0000 16489 4069 ldo1 on control 0000 ldo1_on_m ode 000 0000_0000_0000_0000 16490 406a ldo1 sleep control 0000 ldo1_slp_ mode 000 0000_0001_0000_0000 16491 406b ldo2 control 0 ldo2_hwc _vsel ldo2_flt ldo2_swi 00000 ldo2_lp_m ode 0000_0010_0000_0000 16492 406c ldo2 on control 0000 ldo2_on_m ode 000 0000_0000_0000_0000 16493 406d ldo2 sleep control 0000 ldo2_slp_ mode 000 0000_0001_0000_0000 16494 406e ldo3 control 0 ldo3_hwc _vsel ldo3_flt ldo3_swi 00000 ldo3_lp_m ode 0000_0010_0000_0000 16495 406f ldo3 on control 0000 ldo3_on_m ode 000 0000_0000_0000_0000 16496 4070 ldo3 sleep control 0000 ldo3_slp_ mode 000 0000_0001_0000_0000 16497 4071 ldo4 control 0 ldo4_hwc _vsel ldo4_flt ldo4_swi 00000 ldo4_lp_m ode 0000_0010_0000_0000 16498 4072 ldo4 on control 0000 ldo4_on_m ode 000 0000_0000_0000_0000 16499 4073 ldo4 sleep control 0000 ldo4_slp_ mode 000 0000_0001_0000_0000 16500 4074 ldo5 control 0 ldo5_hwc _vsel ldo5_flt ldo5_swi 00000 ldo5_lp_m ode 0000_0010_0000_0000 16501 4075 ld o5 on control 0000 ldo5_on_m ode 000 0000_0000_0000_0000 16502 4076 ldo5 sleep control 0000 ldo5_slp_ mode 000 0000_0001_0000_0000 16503 4077 ldo6 control 0 ldo6_hwc _vsel ldo6_flt ldo6_swi 00000 ldo6_lp_m ode 0000_0010_0000_0000 ldo5_on_slot[2:0] ldo5_on_vsel[4:0] ldo5_slp_slot[2:0] ldo5_slp_vsel[4:0] ldo6_err_act[1:0] ldo6_hwc_src[1:0] ldo6_hwc_mode[1:0] ldo4_on_vsel[4:0] ldo4_slp_slot[2:0] ldo4_slp_vsel[4:0] ldo5_err_act[1:0] ldo5_hwc_src[1:0] ldo5_hwc_mode[1:0] ldo3_on_slot[2:0] ldo3_on_vsel[4:0] ldo3_slp_slot[2:0] ldo3_slp_vsel[4:0] ldo4_err_act[1:0] ldo4_hwc_src[1:0] ldo4_hwc_mode[1:0] ldo4_on_slot[2:0] ldo2_on_vsel[4:0] ldo2_slp_slot[2:0] ldo2_slp_vsel[4:0] ldo3_err_act[1:0] ldo3_hwc_src[1:0] ldo3_hwc_mode[1:0] ldo1_on_vsel[4:0] ldo1_slp_slot[2:0] ldo1_slp_vsel[4:0] ldo2_err_act[1:0] ldo2_hwc_src[1:0] ldo2_hwc_mode[1:0] epe2_on_slot[2:0] epe2 _ hwc_ s rc[ 1 : 0 ] epe2_slp_slot[2:0] ldo1_err_act[1:0] ldo1_hwc_src[1:0] ldo1_hwc_mode[1:0] ldo1_on_slot[2:0] ldo2_on_slot[2:0] dc4_err_a ct[1:0] dc4_hwc_src[1:0] dc4_ra nge[1:0] epe1_on_slot[2:0] epe1 _ hwc_ s rc[ 1 : 0 ] epe1_slp_slot[2:0] dc3_on_slot[2:0] dc3_on_mode[1:0] dc3_on_v sel[6:2] dc3_on_vsel[1:0] dc3_slp_slot[2:0] dc3_slp_mode[1: 0] dc3_slp_vsel[6:0] dc2_dvs_src[1:0] dc2_dv s_v sel[6:0] dc3_soft_start[1:0] dc3_stnby_lim[1:0] dc3_cap[1:0] dc3_err_a ct[1:0] dc3_hwc_src[1:0] dc3_hwc_mode[1:0] dc2_on_slot[2:0] dc2_on_mode[1:0] dc2_on_v sel[6:2] dc2_on_vsel[1:0] dc2_slp_slot[2:0] dc2_slp_mode[1: 0] dc2_slp_vsel[6:0] dc2_soft_start[1:0] dc2_cap[1:0] dc2_err_a ct[1:0] dc2_hwc_src[1:0] dc2_hwc_mode[1:0] dc2_hc_thr[2:0] dc1_on_vsel[1:0] dc1_slp_slot[2:0] dc1_slp_mode[1: 0] dc1_slp_vsel[6:0] dc1_dvs_src[1:0] dc1_dv s_v sel[6:0] dc1_on_slot[2:0] dc1_on_mode[1:0] dc1_on_v sel[6:2] dc2_rate[1:0] dc2_freq[1:0]
WM8310 pre-production w pp, may 2012, rev 3.1 166 de c ad dr he x a dd r nam e 1514131211109876543210 bin default 16504 4078 ldo6 on control 0000 ldo6_on_m ode 000 0000_0000_0000_0000 16505 4079 ldo6 sleep control 0000 ldo6_slp_ mode 000 0000_0001_0000_0000 16506 407a ldo7 control 0 ldo7_hwc _vsel ldo7_flt ldo7_swi 00000 0 0000_0010_0000_0000 16507 407b ldo7 on control 0000 ldo7_on_m ode 000 0000_0000_0000_0000 16508 407c ldo7 sleep control 0000 ldo7_slp_ mode 000 0000_0001_0000_0000 16509 407d ldo8 control 0 ldo8_hwc _vsel ldo8_flt ldo8_swi 00000 0 0000_0010_0000_0000 16510 407e ldo8 on control 0000 ldo8_on_m ode 000 0000_0000_0000_0000 16511 407f ldo8 sleep control 0000 ldo8_slp_ mode 000 0000_0001_0000_0000 16512 4080 ldo9 control 0 ldo9_hwc _vsel ldo9_flt ldo9_swi 000000 0000_0010_0000_0000 16513 4081 ldo9 on control 0000 ldo9_on_m ode 000 0000_0000_0000_0000 16514 4082 ldo9 sleep control 0000 ldo9_slp_ mode 000 0000_0001_0000_0000 16515 4083 ldo10 control 0 ldo10_hw c_v sel ldo10_flt ldo10_swi 000000 0000_0010_0000_0000 16516 4084 ldo10 on control 0000 ldo10_on_ mode 000 0000_0000_0000_0000 16517 4085 ldo10 sleep control 0000 ldo10_slp _m ode 000 0000_0001_0000_0000 16518 4086 res er v ed 0000000000000000 0000_0000_0000_0000 16519 4087 ldo11 on control ldo11_frc ena 0000 ldo11_vse l_src 000 0000_0000_0000_0000 16520 4088 ldo11 sleep control 000000000 0000_0000_0000_0000 16521 4089 res er v ed 0000000000000000 0000_0000_0000_0000 16522 408a res er v ed 0000000000000000 0000_0000_0000_0000 16523 408b res er v ed 0000000000000000 0000_0000_0000_0000 16524 408c res er v ed 0000000000000000 0000_0000_0000_0000 16525 408d res er v ed 0000000000000000 0000_0000_0000_0000 16526 408e pow er good source 1 000000000000 dc4_ok dc3_ok dc2_ok dc1_ok 0000_0000_0000_0111 16527 408f pow er good source 2 000000 ldo10_ok ldo9_ok ldo8_ok ldo7_ok ldo6_ok ldo5_ok ldo4_ok ldo3_ok ldo2_ok ldo1_ok 0000_0011_1111_1111 16528 4090 clock control 1 clkout_en a 0 clkout_od 00 0 000 clkout_sr c u000_0000_0000_0000 16529 4091 clock control 2 xtal_inh 0 xtal_ena xta l_bkup ena 0000 fll_auto 0000 0001_0000_1000_0000 16530 4092 fll contr ol 1 0000000000000 fll_frac 0 fll_ena 0000_0000_0000_0000 16531 4093 fll contr ol 2 00 00 0000_0000_0000_0000 16532 4094 fll contr ol 3 0000_0000_0000_0000 16533 4095 fll contr ol 4 0 0 0010_1110_1110_0000 16534 4096 fll contr ol 5 00000000000 0 0000_0000_0000_0000 16535 4097 res er v ed 0000000000000000 0000_0000_0000_0000 fll_ctrl_rate[2:0] fll_fratio[2:0] fll_k[15:0] fll_n[9:0] fll_gain[3:0] fll_clk_ref_div[1:0] fll_clk_src[1:0] ldo11_slp_slot[2:0] ldo11_slp_vsel[3:0] clkout_slot[2:0] clkout_slpslot[2:0] fll_a uto_freq[2:0] fll_outdiv[5:0] ldo10_on_slot[2:0] ldo10_on_vsel[4:0] ldo10_slp_slot[2:0] ldo10_slp_vsel[4:0] ldo11_on_slot[2:0] ldo11_on_vsel[3:0] ldo9_on_vsel[4:0] ldo9_slp_slot[2:0] ldo9_slp_vsel[4:0] ldo10_err_act[1:0] ldo10_hwc_src[1:0] ldo10_hwc_mode[1:0] ldo8_on_slot[2:0] ldo8_on_vsel[4:0] ldo8_slp_slot[2:0] ldo8_slp_vsel[4:0] ldo9_err_act[1:0] ldo9_hwc_src[1:0] ldo9_hwc_mode[1:0] ldo9_on_slot[2:0] ldo7_on_vsel[4:0] ldo7_slp_slot[2:0] ldo7_slp_vsel[4:0] ldo8_err_act[1:0] ldo8_hwc_src[1:0] ldo8_hwc_mode[1:0] ldo6_on_slot[2:0] ldo6_on_vsel[4:0] ldo6_slp_slot[2:0] ldo6_slp_vsel[4:0] ldo7_err_act[1:0] ldo7_hwc_src[1:0] ldo7_hwc_mode[1:0] ldo7_on_slot[2:0]
pre-production WM8310 w pp, may 2012, rev 3.1 167 de c addr he x addr nam e 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bin de fault 30720 7800 unique id 1 0000_0000_0000_0000 30721 7801 unique id 2 0000_0000_0000_0000 30722 7802 unique id 3 0000_0000_0000_0000 30723 7803 unique id 4 0000_0000_0000_0000 30724 7804 unique id 5 0000_0000_0000_0000 30725 7805 unique id 6 0000_0000_0000_0000 30726 7806 unique id 7 0000_0000_0000_0000 30727 7807 unique id 8 0000_0000_0000_0000 30728 7808 fac tor y otp id otp_fa ct_ fina l 0000_0000_0000_0000 30729 7809 factory otp 1 0000_0000_0000_0000 30730 780a factory otp 2 0000_0000_0000_0000 30731 780b factory otp 3 00000 0000_0000_0000_0000 30732 780c factory otp 4 00000000 ch_aw 0000_0000_0000_0000 30733 780d factory otp 5 0000000000 0000_0000_0000_0000 30734 780e factory otp 6 0000000000000 dc3_lim_lo w dc2_lim_lo w dc1_lim_lo w 0000_0000_0000_0000 30735 780f res er v ed 0000000000000000 0000_0000_0000_0000 30736 7810 cus tomer otp id otp_a uto_ prog otp_cust_ fina l 0000_0000_0000_0000 30737 7811 dc1 otp contr ol 000 dc1_phase 0000_0000_0000_0000 30738 7812 dc2 otp contr ol 000 dc2_phase 0000_0000_1000_0000 30739 7813 dc3 otp contr ol 00000 dc3_phase 0000_0000_0000_0000 30740 7814 ldo1/2 otp control 0000_0000_0000_0000 30741 7815 ldo3/4 otp control 0000_0000_0000_0000 30742 7816 ldo5/6 otp control 0000_0000_0000_0000 30743 7817 ldo7/8 otp control 0000_0000_0000_0000 30744 7818 ldo9/10 otp control 0000_0000_0000_0000 30745 7819 l do1 1 / epe co n t r o l 0 0000_0000_0000_0000 30746 781a gpio1 otp control gp1_dir gp1_int_m ode gp1_pwr_d om gp1_pol gp1_od gp1_ena clkout_sr c xtal_ena xtal_inh chg_ena 1010_0100_0000_0000 30747 781b gpio2 otp control gp2_dir gp2_int_m ode gp2_pwr_d om gp2_pol gp2_od gp2_ena wdog_ena 1010_0100_0000_0001 30748 781c gpio3 otp control gp3_dir gp3_int_m ode gp3_pwr_d om gp3_pol gp3_od gp3_ena 0 1010_0100_0000_0000 30749 781d gpio4 otp control gp4_dir gp4_int_m ode gp4_pwr_d om gp4_pol gp4_od gp4_ena 1010_0100_0000_1111 30750 781e gpio5 otp control gp5_dir gp5_int_m ode gp5_pwr_d om gp5_pol gp5_od gp5_ena 0 1010_0100_0000_0100 30751 781f gpio6 otp control gp6_dir gp6_int_m ode gp6_pwr_d om gp6_pol gp6_od gp6_ena 0 1010_0100_0000_1010 gp5_pull[1:0] gp5_fn[3:0] usb_ilim[2:0] gp6_pull[1:0] gp6_fn[3:0] sysok_thr[2:0] gp3_pull[1:0] gp3_fn[3:0] fll_auto_freq[2:0] gp4_pull[1:0] gp4_fn[3:0] led1_src[1:0] led2_src[1:0] usb100ma _sta rtup[1:0] gp1_pull[1:0] gp1_fn[3:0] gp2_pull[1:0] gp2_fn[3:0] clkout_slot[2:0] ldo10_on_slot[2:0] ldo10_on_vsel[4:0] ldo9_on_slot[2:0] ldo9_on_vsel[4:0] ldo11_on_slot[2:0] ldo11_on_vsel[3:0] epe2_on_slot[2:0] epe1_on_slot[2:0] ldo6_on_slot[2:0] ldo6_on_vsel[4:0] ldo5_on_slot[2:0] ldo5_on_vsel[4:0] ldo8_on_slot[2:0] ldo8_on_vsel[4:0] ldo7_on_slot[2:0] ldo7_on_vsel[4:0] ldo2_on_slot[2:0] ldo2_on_vsel[4:0] ldo1_on_slot[2:0] ldo1_on_vsel[4:0] ldo4_on_slot[2:0] ldo4_on_vsel[4:0] ldo3_on_slot[2:0] ldo3_on_vsel[4:0] dc2_freq[1:0] dc2_on_vsel[6:2] dc2_cap[1:0] dc3_on_slot[2:0] dc3_on_vsel[6:2] dc3_cap[1:0] child_i2c_a ddr[6: 0] charge_trim[5:0] otp_cust_id[13:0] dc1_on_slot[2:0] dc1_freq[1:0] dc1_on_vsel[6:2] dc1_cap[1:0] dc2_on_slot[2:0] otp_fact_id[14:0] dc3_trim[3:0] dc2_trim[5:0] dc1_trim[5:0] chip_id[15:0] osc_trim[3:0] bg_trim[3:0] lpbg_trim[2:0] unique_id[127:112] unique_id[111:96] unique_id[95:80] unique_id[79:64] unique_id[63:48] unique_id[47:32] unique_id[31:16] unique_id[15:0]
WM8310 pre-production w pp, may 2012, rev 3.1 168 de c addr he x addr nam e 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bin de fault 30752 7820 res er v ed 0000000000000000 0000_0000_0000_0000 30753 7821 res er v ed 0000000000000000 0000_0000_0000_0000 30754 7822 reserved 0000000000000000 0000_0000_0000_0000 30755 7823 res er v ed 0000000000000000 0000_0000_0l0h_h0ll 30756 7824 res er v ed 0000000000000000 0000_0000_0000_0000 30757 7825 res er v ed 0000000000000000 0000_0000_0000_0000 30758 7826 res er v ed 0000000000000000 0000_0000_0000_0000 30759 7827 ice check da ta 0000_0000_0000_0000 ice_valid_data[15:0]
pre-production WM8310 w pp, may 2012, rev 3.1 169 29 register bits by address register address bit label default description refer to r0 (00h) reset id 15:0 chip_id [15:0] 0000_0000 _0000_000 0 writing to this register causes a software reset. the register map contents may be reset, depending on sw_reset_cfg. reading from this register will indicate chip id. register 00h reset id register address bit label default description refer to r1 (01h) revision 15:8 parent_rev [7:0] 0000_0000 the revision number of the parent die 7:0 child_rev [7:0] 0000_0000 the revision number of the child die (when present) register 01h revision register address bit label default description refer to r16384 (4000h) parent id 15:0 parent_id [15:0] 0110_0010 _0000_010 0 the id of the parent die register 4000h parent id register address bit label default description refer to r16385 (4001h) sysvdd control 15:14 syslo_err_ act [1:0] 00 syslo error action selects the action taken when syslo is asserted 00 = interrupt 01 = wake transition 10 = reserved 11 = off transition 11 syslo_sts 0 syslo status 0 = normal 1 = sysvdd is below syslo threshold 6:4 syslo_thr [2:0] 010 syslo threshold (falling sysvdd) this is the falling sysvdd voltage at which syslo will be asserted 000 = 2.8v 001 = 2.9v ? 111 = 3.5v 2:0 sysok_thr [2:0] 101 sysok threshold (rising sysvdd) this is the rising sysvdd voltage at which sysok will be asserted 000 = 2.8v 001 = 2.9v ? 111 = 3.5v note that the sysok hysteresis margin is added to these threshold levels. register 4001h sysvdd control
WM8310 pre-production w pp, may 2012, rev 3.1 170 register address bit label default description refer to r16386 (4002h) thermal monitoring 3 thw_hyst 1 thermal warning hysteresis 0 = 8 degrees c 1 = 16 degrees c 1:0 thw_temp [1:0] 10 thermal warning temperature 00 = 90 degrees c 01 = 100 degrees c 10 = 110 degrees c 11 = 120 degrees c register 4002h thermal monitoring register address bit label default description refer to r16387 (4003h) power state 15 chip_on 0 indicates whether the system is on or off. 0 = off 1 = on (or sleep) off can be commanded by writing chip_on = 0. note that writing chip_on = 1 is not a valid ?on? event, and will not trigger an on transition. 14 chip_slp 0 indicates whether the system is in the sleep state. 0 = not in sleep 1 = sleep wake can be commanded by writing chip_slp = 0. sleep can be commanded by writing chip_slp = 1. 12 ref_lp 0 low power voltage reference control 0 = normal 1 = low power reference mode select note that low power reference mode is only supported when the auxiliary adc is disabled. 11:10 pwrstate_d ly [1:0] 10 power state transition delay 00 = no delay 01 = no delay 10 = 1ms 11 = 10ms 9 swrst_dly 0 software reset delay 0 = no delay 1 = software reset is delayed by pwrstate_dly following the software reset command 5:4 usb100ma_s tartup [1:0] 00 sets the device behaviour when starting up under usb power, when usb_ilim = 010b (100ma) 00 = normal 01 = soft-start 10 = only start if battvdd > 3.1v 11 = only start if battvdd > 3.4v in the 1x modes, if the battery voltage is less than the selected threshold, then the device will enable trickle charge mode instead of executing the start-up request. the start-up request is delayed until the battery voltage threshold has been met. 3 usb_curr_s ts 0 indicates if the usb current limit has been reached 0 = normal 1 = usb current limit
pre-production WM8310 w pp, may 2012, rev 3.1 171 register address bit label default description refer to 2:0 usb_ilim [2:0] 010 sets the usb current limit 000 = 0ma (usb switch is open) 001 = 2.5ma 010 = 100ma 011 = 500ma 100 = 900ma 101 = 1500ma 110 = 1800ma 111 = 550ma note that, when starting up the WM8310 with the usbvdd supply selected, the usb_ilim register must be set to 100ma or higher. register 4003h power state register address bit label default description refer to r16388 (4004h) watchdog 15 wdog_ena 1 watchdog timer enable 0 = disabled 1 = enabled (enables the watchdog; does not reset it) protected by security key. 14 wdog_debu g 0 watchdog pause 0 = disabled 1 = enabled (halts the watchdog timer for system debugging) protected by security key. 13 wdog_rst_s rc 1 watchdog reset source 0 = hardware only 1 = software only protected by security key. 12 wdog_slpe na 0 watchdog sleep enable 0 = disabled 1 = controlled by wdog_ena protected by security key. 11 wdog_rese t 0 watchdog software reset 0 = normal 1 = watchdog reset (resets the watchdog, if wdog_rst_src = 1) 9:8 wdog_seca ct [1:0] 10 secondary action of watchdog timeout (taken after 2 timeout periods) 00 = no action 01 = interrupt 10 = device reset 11 = wake transition protected by security key. 5:4 wdog_prima ct [1:0] 01 primary action of watchdog timeout 00 = no action 01 = interrupt 10 = device reset 11 = wake transition protected by security key.
WM8310 pre-production w pp, may 2012, rev 3.1 172 register address bit label default description refer to 2:0 wdog_to [2:0] 111 watchdog timeout period 000 = 0.256s 001 = 0.512s 010 = 1.024s 011 = 2.048s 100 = 4.096s 101 = 8.192s 110 = 16.384s 111 = 32.768s protected by security key. register 4004h watchdog register address bit label default description refer to r16389 (4005h) on pin control 9:8 on_pin_seca ct [1:0] 01 secondary action of on pi n (taken after 1 timeout period) 00 = interrupt 01 = on request 10 = off request 11 = reserved protected by security key. 5:4 on_pin_prim act [1:0] 00 primary action of on pin 00 = ignore 01 = on request 10 = off request 11 = reserved note that an interrupt is always raised. protected by security key. 3 on_pin_sts 0 current status of on pin 0 = asserted (logic 0) 1 = not asserted (logic 1) 1:0 on_pin_to [1:0] 00 on pin timeout period 00 = 1s 01 = 2s 10 = 4s 11 = 8s protected by security key. register 4005h on pin control register address bit label default description refer to r16390 (4006h) reset control 15 reconfig_a t_on 1 selects if the bootstrap configuration data should be reloaded when an on transition is scheduled 0 = disabled 1 = enabled protected by security key. 13 wall_fet_e na_drv_str 0 sets the drive strength of the wallfetena pin. (note this pin is active low.) 0 = weak drive (500kohm) 1 = strong drive (50kohm)
pre-production WM8310 w pp, may 2012, rev 3.1 173 register address bit label default description refer to 12 batt_fet_en a 0 enables the fet gate functionality on the battfetena pin. (note this pin is active low.) 0 = disabled 1 = enabled note - this bit is reset to 0 when the off power state is entered. 10 sw_reset_c fg 1 software reset configuration. selects whether the register map is reset to default values when software reset occurs. 0 = all registers except rtc and software scratch registers are reset by software reset 1 = register map is not affected by software reset protected by security key. 6 auxrst_slp ena 1 sets the output status of auxiliary reset (gpio) function in sleep 0 = auxiliary reset not asserted 1 = auxiliary reset asserted protected by security key. 5 rst_slp_ms k 1 masks the reset pin input in sleep mode 0 = external reset active in sleep 1 = external reset masked in sleep protected by security key. 4 rst_slpena 1 sets the output status of reset pin in sleep 0 = reset high (not asserted) 1 = reset low (asserted) protected by security key. 1:0 rst_dur [1:0] 11 delay period for releasing reset after on or wake sequence 00 = 3ms 01 = 11ms 10 = 51ms 11 = 101ms protected by security key. register 4006h reset control register address bit label default description refer to r16391 (4007h) control interface 2 autoinc 1 enable auto-increment function 0 = disabled 1 = enabled register 4007h control interface register address bit label default description refer to r16392 (4008h) security key 15:0 security [15:0] 0000_0000 _0000_000 0 security key a value of 9716h must be written to this register to access the user-keyed registers. register 4008h security key
WM8310 pre-production w pp, may 2012, rev 3.1 174 register address bit label default description refer to r16393 (4009h) software scratch 15:0 sw_scratch [15:0] 0000_0000 _0000_000 0 s oftware scratch register for use by the host processor. note that this register?s contents are retained in the backup power state. register 4009h software scratch register address bit label default description refer to r16394 (400ah) otp control 15 otp_prog 0 selects the program device state. 0 = no action 1 = select program mode note that, after program mode has been selected, the chip will remain in program mode until a device reset. protected by security key. 13 otp_mem 1 selects ice or otp memory for program commands. 0 = ice 1 = otp protected by security key. 11 otp_final 0 selects the finalise command, preventing further otp programming. 0 = no action 1 = finalise command protected by security key. 10 otp_verify 0 selects the verify command for the selected otp memory page(s). 0 = no action 1 = verify command protected by security key. 9 otp_write 0 selects write command for the selected otp memory page(s). 0 = no action 1 = write command protected by security key. 8 otp_read 0 selects read command for the selected memory page(s). 0 = no action 1 = read command protected by security key. 7:6 otp_read_l vl [1:0] 00 selects the margin level for read or verify otp commands. 00 = normal 01 = reserved 10 = margin 1 11 = margin 2 protected by security key. 5 otp_bulk 0 selects the number of memory pages for ice / otp commands. 0 = single page 1 = all pages
pre-production WM8310 w pp, may 2012, rev 3.1 175 register address bit label default description refer to 1:0 otp_page [1:0] 00 selects the single memory page for ice / otp commands (when otp_bulk=0). if otp is selected (otp_mem = 1): 00 = page 0 01 = page 1 10 = page 2 11 = page 3 if ice is selected (otp_mem = 0): 00 = page 2 01 = page 3 10 = page 4 11 = reserved register 400ah otp control register address bit label default description refer to r16396 (400ch) gpio level 11 gp12_lvl 0 gpio12 level. when gp12_fn = 0h and gp12_dir = 0, write to this bit to set a gpio output. read from this bit to read gpio input level. when gp12_pol is 0, the register contains the opposite logic level to the external pin. write to this bit to set a gpio output. 10 gp11_lvl 0 gpio11 level. when gp11_fn = 0h and gp11_dir = 0, write to this bit to set a gpio output. read from this bit to read gpio input level. when gp11_pol is 0, the register contains the opposite logic level to the external pin. write to this bit to set a gpio output. 9 gp10_lvl 0 gpio10 level. when gp10_fn = 0h and gp10_dir = 0, write to this bit to set a gpio output. read from this bit to read gpio input level. when gp10_pol is 0, the register contains the opposite logic level to the external pin. write to this bit to set a gpio output. 8 gp9_lvl 0 gpio9 level. when gp9_fn = 0h and gp9_dir = 0, write to this bit to set a gpio output. read from this bit to read gpio input level. when gp9_pol is 0, the regi ster contains the opposite logic level to the external pin. write to this bit to set a gpio output. 7 gp8_lvl 0 gpio8 level. when gp8_fn = 0h and gp8_dir = 0, write to this bit to set a gpio output. read from this bit to read gpio input level. when gp8_pol is 0, the regi ster contains the opposite logic level to the external pin. write to this bit to set a gpio output.
WM8310 pre-production w pp, may 2012, rev 3.1 176 register address bit label default description refer to 6 gp7_lvl 0 gpio7 level. when gp7_fn = 0h and gp7_dir = 0, write to this bit to set a gpio output. read from this bit to read gpio input level. when gp7_pol is 0, the regi ster contains the opposite logic level to the external pin. write to this bit to set a gpio output. 5 gp6_lvl 0 gpio6 level. when gp6_fn = 0h and gp6_dir = 0, write to this bit to set a gpio output. read from this bit to read gpio input level. when gp6_pol is 0, the regi ster contains the opposite logic level to the external pin. write to this bit to set a gpio output. 4 gp5_lvl 0 gpio5 level. when gp5_fn = 0h and gp5_dir = 0, write to this bit to set a gpio output. read from this bit to read gpio input level. when gp5_pol is 0, the regi ster contains the opposite logic level to the external pin. write to this bit to set a gpio output. 3 gp4_lvl 0 gpio4 level. when gp4_fn = 0h and gp4_dir = 0, write to this bit to set a gpio output. read from this bit to read gpio input level. when gp4_pol is 0, the regi ster contains the opposite logic level to the external pin. write to this bit to set a gpio output. 2 gp3_lvl 0 gpio3 level. when gp3_fn = 0h and gp3_dir = 0, write to this bit to set a gpio output. read from this bit to read gpio input level. when gp3_pol is 0, the regi ster contains the opposite logic level to the external pin. write to this bit to set a gpio output. 1 gp2_lvl 0 gpio2 level. when gp2_fn = 0h and gp2_dir = 0, write to this bit to set a gpio output. read from this bit to read gpio input level. when gp2_pol is 0, the regi ster contains the opposite logic level to the external pin. write to this bit to set a gpio output. 0 gp1_lvl 0 gpio1 level. when gp1_fn = 0h and gp1_dir = 0, write to this bit to set a gpio output. read from this bit to read gpio input level. when gp1_pol is 0, the regi ster contains the opposite logic level to the external pin. write to this bit to set a gpio output. register 400ch gpio level
pre-production WM8310 w pp, may 2012, rev 3.1 177 register address bit label default description refer to r16397 (400dh) system status 15 thw_sts 0 thermal warning status 0 = normal 1 = overtemperature warning (warning temperature is set by thw_temp) 10 pwr_src_ba tt 0 battery power source status 0 = battery is not supplying current 1 = battery is supplying current 9 pwr_wall 0 wall adaptor status 0 = wall adaptor voltage not present 1 = wall adaptor voltage is present 8 pwr_usb 0 usb status 0 = usb voltage not present 1 = usb voltage is present 4:0 main_state [4:0] 0_0000 main state machine condition 0_0000 = off 0_0001 = on_chk 0_0010 = otp_dn 0_0011 = read_otp 0_0100 = read_ice 0_0101 = ice_dn 0_0110 = bgdelay 0_0111 = hyst 0_1000 = s_prg_rd_otp 0_1001 = s_prg_otp_dn 0_1010 = pwrdn1 0_1011 = program 0_1100 = prog_dn 0_1101 = prog_otp 0_1110 = vfy_otp 0_1111 = vfy_dn 1_0000 = sd_rd_otp 1_0001 = unused 1_0010 = ice_fail 1_0011 = shutdown 1_0100 = startfail 1_0101 = startup 1_0110 = preactive 1_0111 = xtal_chk 1_1000 = pwrdn2 1_1001 = shut_dly 1_1010 = reset 1_1011 = reset_dly 1_1100 = sleep 1_1101 = sleep_dly 1_1110 = chk_rst 1_1111 = active (on) register 400dh system status
WM8310 pre-production w pp, may 2012, rev 3.1 178 register address bit label default description refer to r16398 (400eh) on source 15 on_trans 0 most recent on/wake event type 0 = wake transition 1 = on transition reset by state machine. 11 on_gpio 0 most recent on/wake event type 0 = not caused by gpio input 1 = caused by gpio input reset by state machine. 10 on_syslo 0 most recent wake event type 0 = not caused by sysvdd 1 = caused by syslo threshold. note that the syslo threshold cannot trigger an on event. reset by state machine. 8 on_chg 0 most recent wake event type 0 = not caused by battery charger 1 = caused by battery charger tbc if this could cause on due to charger plugged in? reset by state machine. 7 on_wdog_t o 0 most recent wake event type 0 = not caused by watchdog timer 1 = caused by watchdog timer reset by state machine. 6 on_sw_req 0 most recent wake event type 0 = not caused by software wake 1 = caused by software wake command (chip_slp = 0) reset by state machine. 5 on_rtc_alm 0 most recent on/wake event type 0 = not caused by rtc alarm 1 = caused by rtc alarm reset by state machine. 4 on_on_pin 0 most recent on/wake event type 0 = not caused by the on pin 1 = caused by the on pin reset by state machine. 3 reset_cnv_ uv 0 most recent on event type 0 = not caused by undervoltage 1 = caused by a device reset due to a converter (ldo or dc-dc) undervoltage condition reset by state machine. 2 reset_sw 0 most recent on event type 0 = not caused by software reset 1 = caused by software reset reset by state machine. 1 reset_hw 0 most recent on event type 0 = not caused by hardware reset 1 = caused by hardware reset reset by state machine. 0 reset_wdo g 0 most recent on event type 0 = not caused by the watchdog 1 = caused by a device reset triggered by the watchdog timer reset by state machine. register 400eh on source
pre-production WM8310 w pp, may 2012, rev 3.1 179 register address bit label default description refer to r16399 (400fh) off source 13 off_intldo_ err 0 most recent off event type 0 = not caused by ldo13 error condition 1 = caused by ldo13 error condition reset by state machine. 12 off_pwr_se q 0 most recent off event type 0 = not caused by power sequence failure 1 = caused by a power sequence failure reset by state machine. 11 off_gpio 0 most recent off event type 0 = not caused by gpio input 1 = caused by gpio input reset by state machine. 10 off_sysvdd 0 most recent off event type 0 = not caused by sysvdd 1 = caused by the syslo or shutdown threshold reset by state machine. 9 off_therr 0 most recent off event type 0 = not caused by temperature 1 = caused by over-temperature reset by state machine. 6 off_sw_req 0 most recent off event type 0 = not caused by software off 1 = caused by software off command (chip_on = 0) reset by state machine. 4 off_on_pin 0 most recent off event type 0 = not caused by the on pin 1 = caused by the on pin reset by state machine. register 400fh off source register address bit label default description refer to r16400 (4010h) system interrupts 15 ps_int 0 power state primary interrupt 0 = no interrupt 1 = interrupt is asserted 14 temp_int 0 thermal primary interrupt 0 = no interrupt 1 = interrupt is asserted 13 gp_int 0 gpio primary interrupt 0 = no interrupt 1 = interrupt is asserted 12 on_pin_int 0 on pin primary interrupt 0 = no interrupt 1 = interrupt is asserted 11 wdog_int 0 watchdog primary interrupt 0 = no interrupt 1 = interrupt is asserted 8 auxadc_int 0 auxadc primary interrupt 0 = no interrupt 1 = interrupt is asserted
WM8310 pre-production w pp, may 2012, rev 3.1 180 register address bit label default description refer to 7 ppm_int 0 power path management primary interrupt 0 = no interrupt 1 = interrupt is asserted 6 cs_int 0 current sink primary interrupt 0 = no interrupt 1 = interrupt is asserted 5 rtc_int 0 real time clock primary interrupt 0 = no interrupt 1 = interrupt is asserted 4 otp_int 0 otp memory primary interrupt 0 = no interrupt 1 = interrupt is asserted 2 chg_int 0 battery charger primary interrupt 0 = no interrupt 1 = interrupt is asserted 1 hc_int 0 high current primary interrupt 0 = no interrupt 1 = interrupt is asserted 0 uv_int 0 undervoltage primary interrupt 0 = no interrupt 1 = interrupt is asserted register 4010h system interrupts register address bit label default description refer to r16401 (4011h) interrupt status 1 15 ppm_syslo_ eint 0 power path syslo interrupt (rising edge triggered) note: cleared when a ?1? is written. 14 ppm_pwr_sr c_eint 0 power path source interrupt (rising edge triggered) note: cleared when a ?1? is written. 13 ppm_usb_cu rr_eint 0 power path usb current interrupt (rising edge triggered) note: cleared when a ?1? is written. 12 on_pin_cint 0 on pin interrupt. (rising and falling edge triggered) note: cleared when a ?1? is written. 11 wdog_to_ei nt 0 watchdog timeout interrupt. (rising edge triggered) note: cleared when a ?1? is written. 8 auxadc_dat a_eint 0 auxadc data ready interrupt (rising edge triggered) note: cleared when a ?1? is written. 7 auxadc_dco mp4_eint 0 auxadc digital comparator 4 interrupt (trigger is controlled by dcmp4_gt) note: cleared when a ?1? is written. 6 auxadc_dco mp3_eint 0 auxadc digital comparator 3 interrupt (trigger is controlled by dcmp3_gt) note: cleared when a ?1? is written.
pre-production WM8310 w pp, may 2012, rev 3.1 181 register address bit label default description refer to 5 auxadc_dco mp2_eint 0 auxadc digital comparator 2 interrupt (trigger is controlled by dcmp2_gt) note: cleared when a ?1? is written. 4 auxadc_dco mp1_eint 0 auxadc digital comparator 1 interrupt (trigger is controlled by dcmp1_gt) note: cleared when a ?1? is written. 3 rtc_per_ein t 0 rtc periodic interrupt (rising edge triggered) note: cleared when a ?1? is written. 2 rtc_alm_ein t 0 rtc alarm interrupt (rising edge triggered) note: cleared when a ?1? is written. 1 temp_thw_c int 0 thermal warning interrupt (rising and falling edge triggered) note: cleared when a ?1? is written. register 4011h interrupt status 1 register address bit label default description refer to r16402 (4012h) interrupt status 2 15 chg_batt_h ot_eint 0 battery hot interrupt (rising edge triggered) note: cleared when a ?1? is written. 14 chg_batt_c old_eint 0 battery cold interrupt (rising edge triggered) note: cleared when a ?1? is written. 13 chg_batt_f ail_eint 0 battery fail interrupt (rising edge triggered) note: cleared when a ?1? is written. 12 chg_ov_eint 0 battery overvoltage interrupt (rising edge triggered) note: cleared when a ?1? is written. 11 chg_end_ei nt 0 battery charge end interrupt (end of charge current threshold reached) (rising edge triggered) note: cleared when a ?1? is written. 10 chg_to_eint 0 battery charge timeout interrupt (charger timer has expired) (rising edge triggered) note: cleared when a ?1? is written. 9 chg_mode_e int 0 battery charge mode interrupt (charger mode has changed) (rising edge triggered) note: cleared when a ?1? is written. 8 chg_start_ eint 0 battery charge start interrupt (charging has started) (rising edge triggered) note: cleared when a ?1? is written. 7 cs2_eint 0 current sink 2 interrupt (rising edge triggered) note: cleared when a ?1? is written. 6 cs1_eint 0 current sink 1 interrupt (rising edge triggered) note: cleared when a ?1? is written.
WM8310 pre-production w pp, may 2012, rev 3.1 182 register address bit label default description refer to 5 otp_cmd_en d_eint 0 otp / ice command end interrupt (rising edge triggered) note: cleared when a ?1? is written. 4 otp_err_ein t 0 otp / ice command fail interrupt (rising edge triggered) note: cleared when a ?1? is written. 2 ps_por_eint 0 power on reset interrupt (rising edge triggered) note: cleared when a ?1? is written. 1 ps_sleep_o ff_eint 0 sleep or off interrupt (power state transition to sleep or off states) (rising edge triggered) note: cleared when a ?1? is written. 0 ps_on_wake _eint 0 on or wake interrupt (power state transition to on state) (rising edge triggered) note: cleared when a ?1? is written. register 4012h interrupt status 2 register address bit label default description refer to r16403 (4013h) interrupt status 3 9 uv_ldo10_ei nt 0 ldo10 undervoltage interrupt (rising edge triggered) note: cleared when a ?1? is written. 8 uv_ldo9_ein t 0 ldo9 undervoltage interrupt (rising edge triggered) note: cleared when a ?1? is written. 7 uv_ldo8_ein t 0 ldo8 undervoltage interrupt (rising edge triggered) note: cleared when a ?1? is written. 6 uv_ldo7_ein t 0 ldo7 undervoltage interrupt (rising edge triggered) note: cleared when a ?1? is written. 5 uv_ldo6_ein t 0 ldo6 undervoltage interrupt (rising edge triggered) note: cleared when a ?1? is written. 4 uv_ldo5_ein t 0 ldo5 undervoltage interrupt (rising edge triggered) note: cleared when a ?1? is written. 3 uv_ldo4_ein t 0 ldo4 undervoltage interrupt (rising edge triggered) note: cleared when a ?1? is written. 2 uv_ldo3_ein t 0 ldo3 undervoltage interrupt (rising edge triggered) note: cleared when a ?1? is written. 1 uv_ldo2_ein t 0 ldo2 undervoltage interrupt (rising edge triggered) note: cleared when a ?1? is written. 0 uv_ldo1_ein t 0 ldo1 undervoltage interrupt (rising edge triggered) note: cleared when a ?1? is written. register 4013h interrupt status 3
pre-production WM8310 w pp, may 2012, rev 3.1 183 register address bit label default description refer to r16404 (4014h) interrupt status 4 9 hc_dc2_eint 0 dc-dc2 high current interrupt (rising edge triggered) note: cleared when a ?1? is written. 8 hc_dc1_eint 0 dc-dc1 high current interrupt (rising edge triggered) note: cleared when a ?1? is written. 3 uv_dc4_eint 0 dc-dc4 undervoltage interrupt (rising edge triggered) note: cleared when a ?1? is written. 2 uv_dc3_eint 0 dc-dc3 undervoltage interrupt (rising edge triggered) note: cleared when a ?1? is written. 1 uv_dc2_eint 0 dc-dc2 undervoltage interrupt (rising edge triggered) note: cleared when a ?1? is written. 0 uv_dc1_eint 0 dc-dc1 undervoltage interrupt (rising edge triggered) note: cleared when a ?1? is written. register 4014h interrupt status 4 register address bit label default description refer to r16405 (4015h) interrupt status 5 11 gp12_eint 0 gpio12 interrupt. (trigger is controlled by gp12_int_mode) note: cleared when a ?1? is written. 10 gp11_eint 0 gpio11 interrupt. (trigger is controlled by gp11_int_mode) note: cleared when a ?1? is written. 9 gp10_eint 0 gpio10 interrupt. (trigger is controlled by gp10_int_mode) note: cleared when a ?1? is written. 8 gp9_eint 0 gpio9 interrupt. (trigger is controlled by gp9_int_mode) note: cleared when a ?1? is written. 7 gp8_eint 0 gpio8 interrupt. (trigger is controlled by gp8_int_mode) note: cleared when a ?1? is written. 6 gp7_eint 0 gpio7 interrupt. (trigger is controlled by gp7_int_mode) note: cleared when a ?1? is written. 5 gp6_eint 0 gpio6 interrupt. (trigger is controlled by gp6_int_mode) note: cleared when a ?1? is written. 4 gp5_eint 0 gpio5 interrupt. (trigger is controlled by gp5_int_mode) note: cleared when a ?1? is written. 3 gp4_eint 0 gpio4 interrupt. (trigger is controlled by gp4_int_mode) note: cleared when a ?1? is written.
WM8310 pre-production w pp, may 2012, rev 3.1 184 register address bit label default description refer to 2 gp3_eint 0 gpio3 interrupt. (trigger is controlled by gp3_int_mode) note: cleared when a ?1? is written. 1 gp2_eint 0 gpio2 interrupt. (trigger is controlled by gp2_int_mode) note: cleared when a ?1? is written. 0 gp1_eint 0 gpio1 interrupt. (trigger is controlled by gp1_int_mode) note: cleared when a ?1? is written. register 4015h interrupt status 5 register address bit label default description refer to r16407 (4017h) irq config 1 irq_od 1 irq pin configuration 0 = cmos 1 = open drain (integrated pull-up) 0 im_irq 0 irq pin output mask 0 = normal 1 = irq output is masked register 4017h irq config register address bit label default description refer to r16408 (4018h) system interrupts mask 15 im_ps_int 1 interrupt mask. 0 = do not mask interrupt. 1 = mask interrupt. default value is 1 (masked) 14 im_temp_int 1 interrupt mask. 0 = do not mask interrupt. 1 = mask interrupt. default value is 1 (masked) 13 im_gp_int 1 interrupt mask. 0 = do not mask interrupt. 1 = mask interrupt. default value is 1 (masked) 12 im_on_pin_in t 1 interrupt mask. 0 = do not mask interrupt. 1 = mask interrupt. default value is 1 (masked) 11 im_wdog_int 1 interrupt mask. 0 = do not mask interrupt. 1 = mask interrupt. default value is 1 (masked) 8 im_auxadc_i nt 1 interrupt mask. 0 = do not mask interrupt. 1 = mask interrupt. default value is 1 (masked)
pre-production WM8310 w pp, may 2012, rev 3.1 185 register address bit label default description refer to 7 im_ppm_int 1 interrupt mask. 0 = do not mask interrupt. 1 = mask interrupt. default value is 1 (masked) 6 im_cs_int 1 interrupt mask. 0 = do not mask interrupt. 1 = mask interrupt. default value is 1 (masked) 5 im_rtc_int 1 interrupt mask. 0 = do not mask interrupt. 1 = mask interrupt. default value is 1 (masked) 4 im_otp_int 1 interrupt mask. 0 = do not mask interrupt. 1 = mask interrupt. default value is 1 (masked) 2 im_chg_int 1 interrupt mask. 0 = do not mask interrupt. 1 = mask interrupt. default value is 1 (masked) 1 im_hc_int 1 interrupt mask. 0 = do not mask interrupt. 1 = mask interrupt. default value is 1 (masked) 0 im_uv_int 1 interrupt mask. 0 = do not mask interrupt. 1 = mask interrupt. default value is 1 (masked) register 4018h system interrupts mask register address bit label default description refer to r16409 (4019h) interrupt status 1 mask 15 im_ppm_sysl o_eint 1 interrupt mask. 0 = do not mask interrupt. 1 = mask interrupt. default value is 1 (masked) 14 im_ppm_pwr _src_eint 1 interrupt mask. 0 = do not mask interrupt. 1 = mask interrupt. default value is 1 (masked) 13 im_ppm_usb_ curr_eint 1 interrupt mask. 0 = do not mask interrupt. 1 = mask interrupt. default value is 1 (masked) 12 im_on_pin_ci nt 1 interrupt mask. 0 = do not mask interrupt. 1 = mask interrupt. default value is 1 (masked) 11 im_wdog_to _eint 1 interrupt mask. 0 = do not mask interrupt. 1 = mask interrupt. default value is 1 (masked)
WM8310 pre-production w pp, may 2012, rev 3.1 186 register address bit label default description refer to 8 im_auxadc_ data_eint 1 interrupt mask. 0 = do not mask interrupt. 1 = mask interrupt. default value is 1 (masked) 7 im_auxadc_ dcomp4_ein t 1 interrupt mask. 0 = do not mask interrupt. 1 = mask interrupt. default value is 1 (masked) 6 im_auxadc_ dcomp3_ein t 1 interrupt mask. 0 = do not mask interrupt. 1 = mask interrupt. default value is 1 (masked) 5 im_auxadc_ dcomp2_ein t 1 interrupt mask. 0 = do not mask interrupt. 1 = mask interrupt. default value is 1 (masked) 4 im_auxadc_ dcomp1_ein t 1 interrupt mask. 0 = do not mask interrupt. 1 = mask interrupt. default value is 1 (masked) 3 im_rtc_per_ eint 1 interrupt mask. 0 = do not mask interrupt. 1 = mask interrupt. default value is 1 (masked) 2 im_rtc_alm_ eint 1 interrupt mask. 0 = do not mask interrupt. 1 = mask interrupt. default value is 1 (masked) 1 im_temp_th w_cint 1 interrupt mask. 0 = do not mask interrupt. 1 = mask interrupt. default value is 1 (masked) register 4019h interrupt status 1 mask register address bit label default description refer to r16410 (401ah) interrupt status 2 mask 15 im_chg_batt _hot_eint 1 interrupt mask. 0 = do not mask interrupt. 1 = mask interrupt. default value is 1 (masked) 14 im_chg_batt _cold_eint 1 interrupt mask. 0 = do not mask interrupt. 1 = mask interrupt. default value is 1 (masked) 13 im_chg_batt _fail_eint 1 interrupt mask. 0 = do not mask interrupt. 1 = mask interrupt. default value is 1 (masked)
pre-production WM8310 w pp, may 2012, rev 3.1 187 register address bit label default description refer to 12 im_chg_ov_ eint 1 interrupt mask. 0 = do not mask interrupt. 1 = mask interrupt. default value is 1 (masked) 11 im_chg_end _eint 1 interrupt mask. 0 = do not mask interrupt. 1 = mask interrupt. default value is 1 (masked) 10 im_chg_to_e int 1 interrupt mask. 0 = do not mask interrupt. 1 = mask interrupt. default value is 1 (masked) 9 im_chg_mod e_eint 1 interrupt mask. 0 = do not mask interrupt. 1 = mask interrupt. default value is 1 (masked) 8 im_chg_sta rt_eint 1 interrupt mask. 0 = do not mask interrupt. 1 = mask interrupt. default value is 1 (masked) 7 im_cs2_eint 1 interrupt mask. 0 = do not mask interrupt. 1 = mask interrupt. default value is 1 (masked) 6 im_cs1_eint 1 interrupt mask. 0 = do not mask interrupt. 1 = mask interrupt. default value is 1 (masked) 5 im_otp_cmd _end_eint 1 interrupt mask. 0 = do not mask interrupt. 1 = mask interrupt. default value is 1 (masked) 4 im_otp_err_ eint 1 interrupt mask. 0 = do not mask interrupt. 1 = mask interrupt. default value is 1 (masked) 2 im_ps_por_e int 1 interrupt mask. 0 = do not mask interrupt. 1 = mask interrupt. default value is 1 (masked) 1 im_ps_sleep _off_eint 1 interrupt mask. 0 = do not mask interrupt. 1 = mask interrupt. default value is 1 (masked) 0 im_ps_on_w ake_eint 1 interrupt mask. 0 = do not mask interrupt. 1 = mask interrupt. default value is 1 (masked) register 401ah interrupt status 2 mask
WM8310 pre-production w pp, may 2012, rev 3.1 188 register address bit label default description refer to r16411 (401bh) interrupt status 3 mask 9 im_uv_ldo10 _eint 1 interrupt mask. 0 = do not mask interrupt. 1 = mask interrupt. default value is 1 (masked) 8 im_uv_ldo9_ eint 1 interrupt mask. 0 = do not mask interrupt. 1 = mask interrupt. default value is 1 (masked) 7 im_uv_ldo8_ eint 1 interrupt mask. 0 = do not mask interrupt. 1 = mask interrupt. default value is 1 (masked) 6 im_uv_ldo7_ eint 1 interrupt mask. 0 = do not mask interrupt. 1 = mask interrupt. default value is 1 (masked) 5 im_uv_ldo6_ eint 1 interrupt mask. 0 = do not mask interrupt. 1 = mask interrupt. default value is 1 (masked) 4 im_uv_ldo5_ eint 1 interrupt mask. 0 = do not mask interrupt. 1 = mask interrupt. default value is 1 (masked) 3 im_uv_ldo4_ eint 1 interrupt mask. 0 = do not mask interrupt. 1 = mask interrupt. default value is 1 (masked) 2 im_uv_ldo3_ eint 1 interrupt mask. 0 = do not mask interrupt. 1 = mask interrupt. default value is 1 (masked) 1 im_uv_ldo2_ eint 1 interrupt mask. 0 = do not mask interrupt. 1 = mask interrupt. default value is 1 (masked) 0 im_uv_ldo1_ eint 1 interrupt mask. 0 = do not mask interrupt. 1 = mask interrupt. default value is 1 (masked) register 401bh interrupt status 3 mask
pre-production WM8310 w pp, may 2012, rev 3.1 189 register address bit label default description refer to r16412 (401ch) interrupt status 4 mask 9 im_hc_dc2_e int 1 interrupt mask. 0 = do not mask interrupt. 1 = mask interrupt. default value is 1 (masked) 8 im_hc_dc1_e int 1 interrupt mask. 0 = do not mask interrupt. 1 = mask interrupt. default value is 1 (masked) 3 im_uv_dc4_e int 1 interrupt mask. 0 = do not mask interrupt. 1 = mask interrupt. default value is 1 (masked) 2 im_uv_dc3_e int 1 interrupt mask. 0 = do not mask interrupt. 1 = mask interrupt. default value is 1 (masked) 1 im_uv_dc2_e int 1 interrupt mask. 0 = do not mask interrupt. 1 = mask interrupt. default value is 1 (masked) 0 im_uv_dc1_e int 1 interrupt mask. 0 = do not mask interrupt. 1 = mask interrupt. default value is 1 (masked) register 401ch interrupt status 4 mask register address bit label default description refer to r16413 (401dh) interrupt status 5 mask 11 im_gp12_ein t 1 interrupt mask. 0 = do not mask interrupt. 1 = mask interrupt. default value is 1 (masked) 10 im_gp11_ein t 1 interrupt mask. 0 = do not mask interrupt. 1 = mask interrupt. default value is 1 (masked) 9 im_gp10_ein t 1 interrupt mask. 0 = do not mask interrupt. 1 = mask interrupt. default value is 1 (masked) 8 im_gp9_eint 1 interrupt mask. 0 = do not mask interrupt. 1 = mask interrupt. default value is 1 (masked) 7 im_gp8_eint 1 interrupt mask. 0 = do not mask interrupt. 1 = mask interrupt. default value is 1 (masked) 6 im_gp7_eint 1 interrupt mask. 0 = do not mask interrupt. 1 = mask interrupt. default value is 1 (masked)
WM8310 pre-production w pp, may 2012, rev 3.1 190 register address bit label default description refer to 5 im_gp6_eint 1 interrupt mask. 0 = do not mask interrupt. 1 = mask interrupt. default value is 1 (masked) 4 im_gp5_eint 1 interrupt mask. 0 = do not mask interrupt. 1 = mask interrupt. default value is 1 (masked) 3 im_gp4_eint 1 interrupt mask. 0 = do not mask interrupt. 1 = mask interrupt. default value is 1 (masked) 2 im_gp3_eint 1 interrupt mask. 0 = do not mask interrupt. 1 = mask interrupt. default value is 1 (masked) 1 im_gp2_eint 1 interrupt mask. 0 = do not mask interrupt. 1 = mask interrupt. default value is 1 (masked) 0 im_gp1_eint 1 interrupt mask. 0 = do not mask interrupt. 1 = mask interrupt. default value is 1 (masked) register 401dh interrupt status 5 mask register address bit label default description refer to r16416 (4020h) rtc write counter 15:0 rtc_wr_cnt [15:0] 0000_0000 _0000_000 0 rtc write counter. this random number is updated on every write to the rtc_time registers. register 4020h rtc write counter register address bit label default description refer to r16417 (4021h) rtc time 1 15:0 rtc_time [15:0] 0000_0000 _0000_000 0 rtc seconds counter (msw) rtc_time increments by 1 every second. this is the 16 msbs. register 4021h rtc time 1 register address bit label default description refer to r16418 (4022h) rtc time 2 15:0 rtc_time [15:0] 0000_0000 _0000_000 0 rtc seconds counter (lsw) rtc_time increments by 1 every second. this is the 16 lsbs. register 4022h rtc time 2
pre-production WM8310 w pp, may 2012, rev 3.1 191 register address bit label default description refer to r16419 (4023h) rtc alarm 1 15:0 rtc_alm [15:0] 0000_0000 _0000_000 0 rtc alarm time (msw) 16 msbs of rtc_alm register 4023h rtc alarm 1 register address bit label default description refer to r16420 (4024h) rtc alarm 2 15:0 rtc_alm [15:0] 0000_0000 _0000_000 0 rtc alarm time (lsw) 16 lsbs of rtc_alm register 4024h rtc alarm 2 register address bit label default description refer to r16421 (4025h) rtc control 15 rtc_valid 0 rtc valid status 0 = rtc_time has not been set since power on reset 1 = rtc_time has been written to since power on reset 14 rtc_sync_b usy 0 rtc busy status 0 = normal 1 = busy the rtc registers should not be written to when rtc_sync_busy = 1. 10 rtc_alm_en a 0 rtc alarm enable 0 = disabled 1 = enabled 6:4 rtc_pint_fr eq [2:0] 000 rtc periodic interrupt timeout period 000 = disabled 001 = 2s 010 = 4s 011 = 8s 100 = 16s 101 = 32s 110 = 64s 111 = 128s register 4025h rtc control register address bit label default description refer to r16422 (4026h) rtc trim 9:0 rtc_trim [9:0] 00_0000_0 000 rtc frequency trim. value is a 10bit fixed point <4,6> 2's complement number. msb scaling = -8hz. the register indicates the e rror (in hz) with respect to the ideal 32768hz) of the input crystal frequency. protected by security key. register 4026h rtc trim
WM8310 pre-production w pp, may 2012, rev 3.1 192 register address bit label default description refer to r16429 (402dh) auxadc data 15:12 aux_data_s rc [3:0] 0000 auxadc data source 0 = reserved 1 = auxadcin1 2 = auxadcin2 3 = auxadcin3 4 = auxadcin4 5 = chip temperature 6 = battery temperature 7 = sysvdd voltage 8 = usb voltage 9 = batt voltage 10 = wall voltage 11 = reserved 12 = reserved 13 = reserved 14 = reserved 15 = reserved 11:0 aux_data [11:0] 0000_0000 _0000 auxadc measurement data voltage (mv) = aux_data x 1.465 chiptemp (c) = (498 - aux_data) / 1.09 batttemp (c) = (value is dependent on ntc thermistor) register 402dh auxadc data register address bit label default description refer to r16430 (402eh) auxadc control 15 aux_ena 0 auxadc enable 0 = disabled 1 = enabled note - this bit is reset to 0 when the off power state is entered. 14 aux_cvt_en a 0 auxadc conversion enable 0 = disabled 1 = enabled in automatic mode, conver sions are enabled by setting this bit. in manual mode (aux_rate = 0), setting this bit will initiate a conversion; the bit is reset automatically after each conversion. 12 aux_slpena 0 auxadc sleep enable 0 = disabled 1 = controlled by aux_ena 5:0 aux_rate [5:0] 00_0000 auxadc conversion rate 0 = manual 1 = 2 samples/s 2 = 4 samples/s 3 = 6 samples/s ? 31 = 62 samples/s 32 = reserved 33 = 16 samples/s 34 = 32 samples/s
pre-production WM8310 w pp, may 2012, rev 3.1 193 register address bit label default description refer to 35 = 48 samples/s ? 63 = 496 samples/s register 402eh auxadc control register address bit label default description refer to r16431 (402fh) auxadc source 9 aux_wall_s el 0 auxadc wall input select 0 = disable wallvdd measurement 1 = enable wallvdd measurement 8 aux_batt_s el 0 auxadc batt input select 0 = disable battvdd measurement 1 = enable battvdd measurement 7 aux_usb_se l 0 auxadc usb input select 0 = disable usbvdd measurement 1 = enable usbvdd measurement 6 aux_sysvdd _sel 0 auxadc sysvdd input select 0 = disable sysvdd measurement 1 = enable sysvdd measurement 5 aux_batt_te mp_sel 0 auxadc battery temp input select 0 = disable battery temp measurement 1 = enable battery temp measurement 4 aux_chip_te mp_sel 0 auxadc chip temp input select 0 = disable chip temp measurement 1 = enable chip temp measurement 3 aux_aux4_s el 0 auxadcin4 input select 0 = disable auxadcin4 measurement 1 = enable auxadcin4 measurement 2 aux_aux3_s el 0 auxadcin3 input select 0 = disable auxadcin3 measurement 1 = enable auxadcin3 measurement 1 aux_aux2_s el 0 auxadcin2 input select 0 = disable auxadcin2 measurement 1 = enable auxadcin2 measurement 0 aux_aux1_s el 0 auxadcin1 input select 0 = disable auxadcin1 measurement 1 = enable auxadcin1 measurement register 402fh auxadc source register address bit label default description refer to r16432 (4030h) comparator control 11 dcomp4_sts 0 digital comparator 4 status 0 = comparator 4 threshold not detected 1 = comparator 4 threshold detected (trigger is controlled by dcmp4_gt) 10 dcomp3_sts 0 digital comparator 3 status 0 = comparator 3 threshold not detected 1 = comparator 3 threshold detected (trigger is controlled by dcmp3_gt)
WM8310 pre-production w pp, may 2012, rev 3.1 194 register address bit label default description refer to 9 dcomp2_sts 0 digital comparator 2 status 0 = comparator 2 threshold not detected 1 = comparator 2 threshold detected (trigger is controlled by dcmp2_gt) 8 dcomp1_sts 0 digital comparator 1 status 0 = comparator 1 threshold not detected 1 = comparator 1 threshold detected (trigger is controlled by dcmp1_gt) 3 dcmp4_ena 0 digital comparator 4 enable 0 = disabled 1 = enabled 2 dcmp3_ena 0 digital comparator 3 enable 0 = disabled 1 = enabled 1 dcmp2_ena 0 digital comparator 2 enable 0 = disabled 1 = enabled 0 dcmp1_ena 0 digital comparator 1 enable 0 = disabled 1 = enabled register 4030h comparator control register address bit label default description refer to r16433 (4031h) comparator 1 15:13 dcmp1_src [2:0] 000 digital comparator 1 source select 0 = usb voltage 1 = auxadcin1 2 = auxadcin2 3 = auxadcin3 4 = auxadcin4 5 = chip temperature 6 = battery temperature 7 = sysvdd voltage 12 dcmp1_gt 0 digital comparator 1 interrupt control 0 = interrupt when less than threshold 1 = interrupt when greater than threshold 11:0 dcmp1_thr [11:0] 0000_0000 _0000 digital comparator 1 threshold (12-bit unsigned binary number; coding is the same as aux_data) register 4031h comparator 1
pre-production WM8310 w pp, may 2012, rev 3.1 195 register address bit label default description refer to r16434 (4032h) comparator 2 15:13 dcmp2_src [2:0] 000 digital comparator 2 source select 0 = wall voltage 1 = auxadcin1 2 = auxadcin2 3 = auxadcin3 4 = auxadcin4 5 = chip temperature 6 = battery temperature 7 = sysvdd voltage 12 dcmp2_gt 0 digital comparator 2 interrupt control 0 = interrupt when less than threshold 1 = interrupt when greater than threshold 11:0 dcmp2_thr [11:0] 0000_0000 _0000 digital comparator 2 threshold (12-bit unsigned binary number; coding is the same as aux_data) register 4032h comparator 2 register address bit label default description refer to r16435 (4033h) comparator 3 15:13 dcmp3_src [2:0] 000 digital comparator 3 source select 0 = batt voltage 1 = auxadcin1 2 = auxadcin2 3 = auxadcin3 4 = auxadcin4 5 = chip temperature 6 = battery temperature 7 = sysvdd voltage 12 dcmp3_gt 0 digital comparator 3 interrupt control 0 = interrupt when less than threshold 1 = interrupt when greater than threshold 11:0 dcmp3_thr [11:0] 0000_0000 _0000 digital comparator 3 threshold (12-bit unsigned binary number; coding is the same as aux_data) register 4033h comparator 3 register address bit label default description refer to r16436 (4034h) comparator 4 15:13 dcmp4_src [2:0] 000 digital comparator 4 source select 0 = reserved 1 = auxadcin1 2 = auxadcin2 3 = auxadcin3 4 = auxadcin4 5 = chip temperature 6 = battery temperature 7 = sysvdd voltage 12 dcmp4_gt 0 digital comparator 4 interrupt control 0 = interrupt when less than threshold 1 = interrupt when greater than threshold
WM8310 pre-production w pp, may 2012, rev 3.1 196 register address bit label default description refer to 11:0 dcmp4_thr [11:0] 0000_0000 _0000 digital comparator 4 threshold (12-bit unsigned binary number; coding is the same as aux_data) register 4034h comparator 4 register address bit label default description refer to r16440 (4038h) gpio1 control 15 gp1_dir 1 gpio1 pin direction 0 = output 1 = input 14:13 gp1_pull [1:0] 01 gpio1 pull-up / pull-down configuration 00 = no pull resistor 01 = pull-down enabled 10 = pull-up enabled 11 = reserved 12 gp1_int_mod e 0 gpio1 interrupt mode 0 = gpio interrupt is rising edge triggered (if gp1_pol=1) or falling edge triggered (if gp1_pol=0) 1 = gpio interrupt is triggered on rising and falling edges 11 gp1_pwr_do m 0 gpio1 power domain select 0 = dbvdd 1 = pmicvdd (ldo12) 10 gp1_pol 1 gpio1 polarity select 0 = inverted (active low) 1 = non-inverted (active high) 9 gp1_od 0 gpio1 output pin configuration 0 = cmos 1 = open drain 7 gp1_ena 0 gpio1 enable control 0 = gpio pin is tri-stated 1 = normal operation 3:0 gp1_fn [3:0] 0000 gpio1 pin function input functions: 0 = gpio input (long de-bounce) 1 = gpio input 2 = power on/off request 3 = sleep/wake request 4 = sleep/wake request (long de-bounce) 5 = sleep request 6 = power on request 7 = watchdog reset input 8 = dvs1 input 9 = dvs2 input 10 = hw enable1 input 11 = hw enable2 input 12 = hw control1 input 13 = hw control2 input 14 = hw control1 input (long de-bounce) 15 = hw control2 input (long de-bounce) output functions:
pre-production WM8310 w pp, may 2012, rev 3.1 197 register address bit label default description refer to 0 = gpio output 1 = 32.768khz oscillator output 2 = on state 3 = sleep state 4 = power state change 5 = reserved 6 = reserved 7 = reserved 8 = dc-dc1 dvs done 9 = dc-dc2 dvs done 10 = external power enable1 11 = external power enable2 12 = system supply good (sysok) 13 = converter power good (pwr_good) 14 = external power clock (2mhz) 15 = auxiliary reset register 4038h gpio1 control register address bit label default description refer to r16441 (4039h) gpio2 control 15 gp2_dir 1 gpio2 pin direction 0 = output 1 = input 14:13 gp2_pull [1:0] 01 gpio2 pull-up / pull-down configuration 00 = no pull resistor 01 = pull-down enabled 10 = pull-up enabled 11 = reserved 12 gp2_int_mod e 0 gpio2 interrupt mode 0 = gpio interrupt is rising edge triggered (if gp2_pol=1) or falling edge triggered (if gp2_pol=0) 1 = gpio interrupt is triggered on rising and falling edges 11 gp2_pwr_do m 0 gpio2 power domain select 0 = dbvdd 1 = pmicvdd (ldo12) 10 gp2_pol 1 gpio2 polarity select 0 = inverted (active low) 1 = non-inverted (active high) 9 gp2_od 0 gpio2 output pin configuration 0 = cmos 1 = open drain 7 gp2_ena 0 gpio2 enable control 0 = gpio pin is tri-stated 1 = normal operation 3:0 gp2_fn [3:0] 0000 gpio2 pin function input functions: 0 = gpio input (long de-bounce) 1 = gpio input 2 = power on/off request 3 = sleep/wake request 4 = sleep/wake request (long de-bounce)
WM8310 pre-production w pp, may 2012, rev 3.1 198 register address bit label default description refer to 5 = sleep request 6 = power on request 7 = watchdog reset input 8 = dvs1 input 9 = dvs2 input 10 = hw enable1 input 11 = hw enable2 input 12 = hw control1 input 13 = hw control2 input 14 = hw control1 input (long de-bounce) 15 = hw control2 input (long de-bounce) output functions: 0 = gpio output 1 = 32.768khz oscillator output 2 = on state 3 = sleep state 4 = power state change 5 = reserved 6 = reserved 7 = reserved 8 = dc-dc1 dvs done 9 = dc-dc2 dvs done 10 = external power enable1 11 = external power enable2 12 = system supply good (sysok) 13 = converter power good (pwr_good) 14 = external power clock (2mhz) 15 = auxiliary reset register 4039h gpio2 control register address bit label default description refer to r16442 (403ah) gpio3 control 15 gp3_dir 1 gpio3 pin direction 0 = output 1 = input 14:13 gp3_pull [1:0] 01 gpio3 pull-up / pull-down configuration 00 = no pull resistor 01 = pull-down enabled 10 = pull-up enabled 11 = reserved 12 gp3_int_mod e 0 gpio3 interrupt mode 0 = gpio interrupt is rising edge triggered (if gp3_pol=1) or falling edge triggered (if gp3_pol=0) 1 = gpio interrupt is triggered on rising and falling edges 11 gp3_pwr_do m 0 gpio3 power domain select 0 = dbvdd 1 = pmicvdd (ldo12) 10 gp3_pol 1 gpio3 polarity select 0 = inverted (active low) 1 = non-inverted (active high)
pre-production WM8310 w pp, may 2012, rev 3.1 199 register address bit label default description refer to 9 gp3_od 0 gpio3 output pin configuration 0 = cmos 1 = open drain 7 gp3_ena 0 gpio3 enable control 0 = gpio pin is tri-stated 1 = normal operation 3:0 gp3_fn [3:0] 0000 gpio3 pin function input functions: 0 = gpio input (long de-bounce) 1 = gpio input 2 = power on/off request 3 = sleep/wake request 4 = sleep/wake request (long de-bounce) 5 = sleep request 6 = power on request 7 = watchdog reset input 8 = dvs1 input 9 = dvs2 input 10 = hw enable1 input 11 = hw enable2 input 12 = hw control1 input 13 = hw control2 input 14 = hw control1 input (long de-bounce) 15 = hw control2 input (long de-bounce) output functions: 0 = gpio output 1 = 32.768khz oscillator output 2 = on state 3 = sleep state 4 = power state change 5 = reserved 6 = reserved 7 = reserved 8 = dc-dc1 dvs done 9 = dc-dc2 dvs done 10 = external power enable1 11 = external power enable2 12 = system supply good (sysok) 13 = converter power good (pwr_good) 14 = external power clock (2mhz) 15 = auxiliary reset register 403ah gpio3 control
WM8310 pre-production w pp, may 2012, rev 3.1 200 register address bit label default description refer to r16443 (403bh) gpio4 control 15 gp4_dir 1 gpio4 pin direction 0 = output 1 = input 14:13 gp4_pull [1:0] 01 gpio4 pull-up / pull-down configuration 00 = no pull resistor 01 = pull-down enabled 10 = pull-up enabled 11 = reserved 12 gp4_int_mod e 0 gpio4 interrupt mode 0 = gpio interrupt is rising edge triggered (if gp4_pol=1) or falling edge triggered (if gp4_pol=0) 1 = gpio interrupt is triggered on rising and falling edges 11 gp4_pwr_do m 0 gpio4 power domain select 0 = dbvdd 1 = sysvdd 10 gp4_pol 1 gpio4 polarity select 0 = inverted (active low) 1 = non-inverted (active high) 9 gp4_od 0 gpio4 output pin configuration 0 = cmos 1 = open drain 7 gp4_ena 0 gpio4 enable control 0 = gpio pin is tri-stated 1 = normal operation 3:0 gp4_fn [3:0] 0000 gpio4 pin function input functions: 0 = gpio input (long de-bounce) 1 = gpio input 2 = power on/off request 3 = sleep/wake request 4 = sleep/wake request (long de-bounce) 5 = sleep request 6 = power on request 7 = watchdog reset input 8 = dvs1 input 9 = dvs2 input 10 = hw enable1 input 11 = hw enable2 input 12 = hw control1 input 13 = hw control2 input 14 = hw control1 input (long de-bounce) 15 = hw control2 input (long de-bounce) output functions: 0 = gpio output 1 = 32.768khz oscillator output 2 = on state 3 = sleep state 4 = power state change 5 = reserved 6 = reserved 7 = reserved
pre-production WM8310 w pp, may 2012, rev 3.1 201 register address bit label default description refer to 8 = dc-dc1 dvs done 9 = dc-dc2 dvs done 10 = external power enable1 11 = external power enable2 12 = system supply good (sysok) 13 = converter power good (pwr_good) 14 = external power clock (2mhz) 15 = auxiliary reset register 403bh gpio4 control register address bit label default description refer to r16444 (403ch) gpio5 control 15 gp5_dir 1 gpio5 pin direction 0 = output 1 = input 14:13 gp5_pull [1:0] 01 gpio5 pull-up / pull-down configuration 00 = no pull resistor 01 = pull-down enabled 10 = pull-up enabled 11 = reserved 12 gp5_int_mod e 0 gpio5 interrupt mode 0 = gpio interrupt is rising edge triggered (if gp5_pol=1) or falling edge triggered (if gp5_pol=0) 1 = gpio interrupt is triggered on rising and falling edges 11 gp5_pwr_do m 0 gpio5 power domain select 0 = dbvdd 1 = sysvdd 10 gp5_pol 1 gpio5 polarity select 0 = inverted (active low) 1 = non-inverted (active high) 9 gp5_od 0 gpio5 output pin configuration 0 = cmos 1 = open drain 7 gp5_ena 0 gpio5 enable control 0 = gpio pin is tri-stated 1 = normal operation 3:0 gp5_fn [3:0] 0000 gpio5 pin function input functions: 0 = gpio input (long de-bounce) 1 = gpio input 2 = power on/off request 3 = sleep/wake request 4 = sleep/wake request (long de-bounce) 5 = sleep request 6 = power on request 7 = watchdog reset input 8 = dvs1 input 9 = dvs2 input 10 = hw enable1 input 11 = hw enable2 input 12 = hw control1 input
WM8310 pre-production w pp, may 2012, rev 3.1 202 register address bit label default description refer to 13 = hw control2 input 14 = hw control1 input (long de-bounce) 15 = hw control2 input (long de-bounce) output functions: 0 = gpio output 1 = 32.768khz oscillator output 2 = on state 3 = sleep state 4 = power state change 5 = reserved 6 = reserved 7 = reserved 8 = dc-dc1 dvs done 9 = dc-dc2 dvs done 10 = external power enable1 11 = external power enable2 12 = system supply good (sysok) 13 = converter power good (pwr_good) 14 = external power clock (2mhz) 15 = auxiliary reset register 403ch gpio5 control register address bit label default description refer to r16445 (403dh) gpio6 control 15 gp6_dir 1 gpio6 pin direction 0 = output 1 = input 14:13 gp6_pull [1:0] 01 gpio6 pull-up / pull-down configuration 00 = no pull resistor 01 = pull-down enabled 10 = pull-up enabled 11 = reserved 12 gp6_int_mod e 0 gpio6 interrupt mode 0 = gpio interrupt is rising edge triggered (if gp6_pol=1) or falling edge triggered (if gp6_pol=0) 1 = gpio interrupt is triggered on rising and falling edges 11 gp6_pwr_do m 0 gpio6 power domain select 0 = dbvdd 1 = sysvdd 10 gp6_pol 1 gpio6 polarity select 0 = inverted (active low) 1 = non-inverted (active high) 9 gp6_od 0 gpio6 output pin configuration 0 = cmos 1 = open drain 7 gp6_ena 1 gpio6 enable control 0 = gpio pin is tri-stated 1 = normal operation
pre-production WM8310 w pp, may 2012, rev 3.1 203 register address bit label default description refer to 3:0 gp6_fn [3:0] 0000 gpio6 pin function input functions: 0 = gpio input (long de-bounce) 1 = gpio input 2 = power on/off request 3 = sleep/wake request 4 = sleep/wake request (long de-bounce) 5 = sleep request 6 = power on request 7 = watchdog reset input 8 = dvs1 input 9 = dvs2 input 10 = hw enable1 input 11 = hw enable2 input 12 = hw control1 input 13 = hw control2 input 14 = hw control1 input (long de-bounce) 15 = hw control2 input (long de-bounce) output functions: 0 = gpio output 1 = 32.768khz oscillator output 2 = on state 3 = sleep state 4 = power state change 5 = reserved 6 = reserved 7 = reserved 8 = dc-dc1 dvs done 9 = dc-dc2 dvs done 10 = external power enable1 11 = external power enable2 12 = system supply good (sysok) 13 = converter power good (pwr_good) 14 = external power clock (2mhz) 15 = auxiliary reset register 403dh gpio6 control register address bit label default description refer to r16446 (403eh) gpio7 control 15 gp7_dir 1 gpio7 pin direction 0 = output 1 = input 14:13 gp7_pull [1:0] 01 gpio7 pull-up / pull-down configuration 00 = no pull resistor 01 = pull-down enabled 10 = pull-up enabled 11 = reserved 12 gp7_int_mod e 0 gpio7 interrupt mode 0 = gpio interrupt is rising edge triggered (if gp7_pol=1) or falling edge triggered (if gp7_pol=0) 1 = gpio interrupt is triggered on rising and falling
WM8310 pre-production w pp, may 2012, rev 3.1 204 register address bit label default description refer to edges 11 gp7_pwr_do m 0 gpio7 power domain select 0 = dbvdd 1 = pmicvdd (ldo12) 10 gp7_pol 1 gpio7 polarity select 0 = inverted (active low) 1 = non-inverted (active high) 9 gp7_od 0 gpio7 output pin configuration 0 = cmos 1 = open drain 7 gp7_ena 0 gpio7 enable control 0 = gpio pin is tri-stated 1 = normal operation 3:0 gp7_fn [3:0] 0000 gpio7 pin function input functions: 0 = gpio input (long de-bounce) 1 = gpio input 2 = power on/off request 3 = sleep/wake request 4 = sleep/wake request (long de-bounce) 5 = sleep request 6 = power on request 7 = watchdog reset input 8 = dvs1 input 9 = dvs2 input 10 = hw enable1 input 11 = hw enable2 input 12 = hw control1 input 13 = hw control2 input 14 = hw control1 input (long de-bounce) 15 = hw control2 input (long de-bounce) output functions: 0 = gpio output 1 = 32.768khz oscillator output 2 = on state 3 = sleep state 4 = power state change 5 = reserved 6 = reserved 7 = reserved 8 = dc-dc1 dvs done 9 = dc-dc2 dvs done 10 = external power enable1 11 = external power enable2 12 = system supply good (sysok) 13 = converter power good (pwr_good) 14 = external power clock (2mhz) 15 = auxiliary reset register 403eh gpio7 control
pre-production WM8310 w pp, may 2012, rev 3.1 205 register address bit label default description refer to r16447 (403fh) gpio8 control 15 gp8_dir 1 gpio8 pin direction 0 = output 1 = input 14:13 gp8_pull [1:0] 01 gpio8 pull-up / pull-down configuration 00 = no pull resistor 01 = pull-down enabled 10 = pull-up enabled 11 = reserved 12 gp8_int_mod e 0 gpio8 interrupt mode 0 = gpio interrupt is rising edge triggered (if gp8_pol=1) or falling edge triggered (if gp8_pol=0) 1 = gpio interrupt is triggered on rising and falling edges 11 gp8_pwr_do m 0 gpio8 power domain select 0 = dbvdd 1 = pmicvdd (ldo12) 10 gp8_pol 1 gpio8 polarity select 0 = inverted (active low) 1 = non-inverted (active high) 9 gp8_od 0 gpio8 output pin configuration 0 = cmos 1 = open drain 7 gp8_ena 1 gpio8 enable control 0 = gpio pin is tri-stated 1 = normal operation 3:0 gp8_fn [3:0] 0000 gpio8 pin function input functions: 0 = gpio input (long de-bounce) 1 = gpio input 2 = power on/off request 3 = sleep/wake request 4 = sleep/wake request (long de-bounce) 5 = sleep request 6 = power on request 7 = watchdog reset input 8 = dvs1 input 9 = dvs2 input 10 = hw enable1 input 11 = hw enable2 input 12 = hw control1 input 13 = hw control2 input 14 = hw control1 input (long de-bounce) 15 = hw control2 input (long de-bounce) output functions: 0 = gpio output 1 = 32.768khz oscillator output 2 = on state 3 = sleep state 4 = power state change 5 = reserved 6 = reserved 7 = reserved
WM8310 pre-production w pp, may 2012, rev 3.1 206 register address bit label default description refer to 8 = dc-dc1 dvs done 9 = dc-dc2 dvs done 10 = external power enable1 11 = external power enable2 12 = system supply good (sysok) 13 = converter power good (pwr_good) 14 = external power clock (2mhz) 15 = auxiliary reset register 403fh gpio8 control register address bit label default description refer to r16448 (4040h) gpio9 control 15 gp9_dir 1 gpio9 pin direction 0 = output 1 = input 14:13 gp9_pull [1:0] 01 gpio9 pull-up / pull-down configuration 00 = no pull resistor 01 = pull-down enabled 10 = pull-up enabled 11 = reserved 12 gp9_int_mod e 0 gpio9 interrupt mode 0 = gpio interrupt is rising edge triggered (if gp9_pol=1) or falling edge triggered (if gp9_pol=0) 1 = gpio interrupt is triggered on rising and falling edges 11 gp9_pwr_do m 0 gpio9 power domain select 0 = dbvdd 1 = pmicvdd (ldo12) 10 gp9_pol 1 gpio9 polarity select 0 = inverted (active low) 1 = non-inverted (active high) 9 gp9_od 0 gpio9 output pin configuration 0 = cmos 1 = open drain 7 gp9_ena 0 gpio9 enable control 0 = gpio pin is tri-stated 1 = normal operation 3:0 gp9_fn [3:0] 0000 gpio9 pin function input functions: 0 = gpio input (long de-bounce) 1 = gpio input 2 = power on/off request 3 = sleep/wake request 4 = sleep/wake request (long de-bounce) 5 = sleep request 6 = power on request 7 = watchdog reset input 8 = dvs1 input 9 = dvs2 input 10 = hw enable1 input 11 = hw enable2 input 12 = hw control1 input
pre-production WM8310 w pp, may 2012, rev 3.1 207 register address bit label default description refer to 13 = hw control2 input 14 = hw control1 input (long de-bounce) 15 = hw control2 input (long de-bounce) output functions: 0 = gpio output 1 = 32.768khz oscillator output 2 = on state 3 = sleep state 4 = power state change 5 = reserved 6 = reserved 7 = reserved 8 = dc-dc1 dvs done 9 = dc-dc2 dvs done 10 = external power enable1 11 = external power enable2 12 = system supply good (sysok) 13 = converter power good (pwr_good) 14 = external power clock (2mhz) 15 = auxiliary reset register 4040h gpio9 control register address bit label default description refer to r16449 (4041h) gpio10 control 15 gp10_dir 1 gpio10 pin direction 0 = output 1 = input 14:13 gp10_pull [1:0] 01 gpio10 pull-up / pull-down configuration 00 = no pull resistor 01 = pull-down enabled 10 = pull-up enabled 11 = reserved 12 gp10_int_mo de 0 gpio10 interrupt mode 0 = gpio interrupt is rising edge triggered (if gp10_pol=1) or falling edge triggered (if gp10_pol=0) 1 = gpio interrupt is triggered on rising and falling edges 11 gp10_pwr_d om 0 gpio10 power domain select 0 = dbvdd 1 = sysvdd 10 gp10_pol 1 gpio10 polarity select 0 = inverted (active low) 1 = non-inverted (active high) 9 gp10_od 0 gpio10 output pin configuration 0 = cmos 1 = open drain 7 gp10_ena 0 gpio10 enable control 0 = gpio pin is tri-stated 1 = normal operation
WM8310 pre-production w pp, may 2012, rev 3.1 208 register address bit label default description refer to 3:0 gp10_fn [3:0] 0000 gpio10 pin function input functions: 0 = gpio input (long de-bounce) 1 = gpio input 2 = power on/off request 3 = sleep/wake request 4 = sleep/wake request (long de-bounce) 5 = sleep request 6 = power on request 7 = watchdog reset input 8 = dvs1 input 9 = dvs2 input 10 = hw enable1 input 11 = hw enable2 input 12 = hw control1 input 13 = hw control2 input 14 = hw control1 input (long de-bounce) 15 = hw control2 input (long de-bounce) output functions: 0 = gpio output 1 = 32.768khz oscillator output 2 = on state 3 = sleep state 4 = power state change 5 = reserved 6 = reserved 7 = reserved 8 = dc-dc1 dvs done 9 = dc-dc2 dvs done 10 = external power enable1 11 = external power enable2 12 = system supply good (sysok) 13 = converter power good (pwr_good) 14 = external power clock (2mhz) 15 = auxiliary reset register 4041h gpio10 control register address bit label default description refer to r16450 (4042h) gpio11 control 15 gp11_dir 1 gpio11 pin direction 0 = output 1 = input 14:13 gp11_pull [1:0] 01 gpio11 pull-up / pull-down configuration 00 = no pull resistor 01 = pull-down enabled 10 = pull-up enabled 11 = reserved 12 gp11_int_mo de 0 gpio11 interrupt mode 0 = gpio interrupt is rising edge triggered (if gp11_pol=1) or falling edge triggered (if gp11_pol=0)
pre-production WM8310 w pp, may 2012, rev 3.1 209 register address bit label default description refer to 1 = gpio interrupt is triggered on rising and falling edges 11 gp11_pwr_d om 0 gpio11 power domain select 0 = dbvdd 1 = sysvdd 10 gp11_pol 1 gpio11 polarity select 0 = inverted (active low) 1 = non-inverted (active high) 9 gp11_od 0 gpio11 output pin configuration 0 = cmos 1 = open drain 7 gp11_ena 0 gpio11 enable control 0 = gpio pin is tri-stated 1 = normal operation 3:0 gp11_fn [3:0] 0000 gpio11 pin function input functions: 0 = gpio input (long de-bounce) 1 = gpio input 2 = power on/off request 3 = sleep/wake request 4 = sleep/wake request (long de-bounce) 5 = sleep request 6 = power on request 7 = watchdog reset input 8 = dvs1 input 9 = dvs2 input 10 = hw enable1 input 11 = hw enable2 input 12 = hw control1 input 13 = hw control2 input 14 = hw control1 input (long de-bounce) 15 = hw control2 input (long de-bounce) output functions: 0 = gpio output 1 = 32.768khz oscillator output 2 = on state 3 = sleep state 4 = power state change 5 = reserved 6 = reserved 7 = reserved 8 = dc-dc1 dvs done 9 = dc-dc2 dvs done 10 = external power enable1 11 = external power enable2 12 = system supply good (sysok) 13 = converter power good (pwr_good) 14 = external power clock (2mhz) 15 = auxiliary reset register 4042h gpio11 control
WM8310 pre-production w pp, may 2012, rev 3.1 210 register address bit label default description refer to r16451 (4043h) gpio12 control 15 gp12_dir 1 gpio12 pin direction 0 = output 1 = input 14:13 gp12_pull [1:0] 01 gpio12 pull-up / pull-down configuration 00 = no pull resistor 01 = pull-down enabled 10 = pull-up enabled 11 = reserved 12 gp12_int_mo de 0 gpio12 interrupt mode 0 = gpio interrupt is rising edge triggered (if gp12_pol=1) or falling edge triggered (if gp12_pol=0) 1 = gpio interrupt is triggered on rising and falling edges 11 gp12_pwr_d om 0 gpio12 power domain select 0 = dbvdd 1 = sysvdd 10 gp12_pol 1 gpio12 polarity select 0 = inverted (active low) 1 = non-inverted (active high) 9 gp12_od 0 gpio12 output pin configuration 0 = cmos 1 = open drain 7 gp12_ena 0 gpio12 enable control 0 = gpio pin is tri-stated 1 = normal operation
pre-production WM8310 w pp, may 2012, rev 3.1 211 register address bit label default description refer to 3:0 gp12_fn [3:0] 0000 gpio12 pin function input functions: 0 = gpio input (long de-bounce) 1 = gpio input 2 = power on/off request 3 = sleep/wake request 4 = sleep/wake request (long de-bounce) 5 = sleep request 6 = power on request 7 = watchdog reset input 8 = dvs1 input 9 = dvs2 input 10 = hw enable1 input 11 = hw enable2 input 12 = hw control1 input 13 = hw control2 input 14 = hw control1 input (long de-bounce) 15 = hw control2 input (long de-bounce) output functions: 0 = gpio output 1 = 32.768khz oscillator output 2 = on state 3 = sleep state 4 = power state change 5 = reserved 6 = reserved 7 = reserved 8 = dc-dc1 dvs done 9 = dc-dc2 dvs done 10 = external power enable1 11 = external power enable2 12 = system supply good (sysok) 13 = converter power good (pwr_good) 14 = external power clock (2mhz) 15 = auxiliary reset register 4043h gpio12 control register address bit label default description refer to r16456 (4048h) charger control 1 15 chg_ena 0 battery charger enable 0 = disable 1 = enable protected by security key. 14 chg_frc 0 force charging 0 = normal behaviour 1 = force charging chg_frc enables charging even if the battery voltage is above the restart threshold. it is not recommended to use this feature; there are safety implications in its use. this bit should be reset to 0 after charging has started. host processor should monitor chg_mode_eint to
WM8310 pre-production w pp, may 2012, rev 3.1 212 register address bit label default description refer to confirm that charging has started. protected by security key. 12:10 chg_iterm [2:0] 000 battery end of charge current threshold 000 = 20ma 001 = 30ma 010 = 40ma 011 = 50ma 100 = 60ma 101 = 70ma 110 = 80ma 111 = 90ma protected by security key. 5 chg_fast 0 battery fast charge enable 0 = disable 1 = enable protected by security key. 1 chg_imon_e na 0 enable battery charge current monitor at auxadcin1. 0 = disabled 1 = enabled (note - a resistor is required between auxadcin1 and gnd in order to measure the charge current using the auxadc. the recommended resistor value is 10k.) protected by security key. 0 chg_chip_te mp_mon 1 battery charger thermal warning select 0 = thermal warning is ignored 1 = thermal warning pauses battery charger protected by security key. register 4048h charger control 1 register address bit label default description refer to r16457 (4049h) charger control 2 14 chg_off_ms k 0 battery charger off mask select 0 = off requests not masked 1 = off requests masked during charging protected by security key. 11:8 chg_time [3:0] 0110 battery charger timeout 0000 = 60min 0001 = 90min 0010 = 120min 0011 = 150min 0100 = 180min 0101 = 210min 0110 = 240min 0111 = 270min 1000 = 300min 1001 = 330min 1010 = 360min 1011 = 390min 1100 = 420min 1101 = 450min 1110 = 480min 1111 = 510min
pre-production WM8310 w pp, may 2012, rev 3.1 213 register address bit label default description refer to protected by security key. 7:6 chg_trkl_ili m [1:0] 00 battery trickle charge current limit 00 = 50ma 01 = 100ma 10 = 150ma 11 = 200ma protected by security key. 5:4 chg_vsel [1:0] 00 battery charger target voltage 00 = 4.05v 01 = 4.10v 10 = 4.15v 11 = 4.20v note that incorrect setting of this register may lead to a safety hazard condition. protected by security key. 3:0 chg_fast_ili m [3:0] 0010 battery fast charge current limit 0000 = 0ma 0001 = 50ma 0010 = 100ma 0011 = 150ma 0100 = 200ma 0101 = 250ma 0110 = 300ma 0111 = 350ma 1000 = 400ma 1001 = 450ma 1010 = 500ma 1011 = 600ma 1100 = 700ma 1101 = 800ma 1110 = 900ma 1111 = 1000ma protected by security key. register 4049h charger control 2 register address bit label default description refer to r16458 (404ah) charger status 15 batt_ov_st s 0 battery overvoltage status 0 = normal 1 = battery overvoltage 14:12 chg_state [2:0] 000 battery charger state 000 = off 001 = trickle charge 010 = fast charge 011 = trickle charge overtemperature 100 = fast charge overtemperature 101 = defective 110 = reserved 111 = reserved 11 batt_hot_st s 0 battery hot status 0 = normal 1 = battery hot
WM8310 pre-production w pp, may 2012, rev 3.1 214 register address bit label default description refer to 10 batt_cold_ sts 0 battery cold status 0 = normal 1 = battery cold 9 chg_topoff 0 battery charger c onstant-voltage charge mode status 0 = constant-voltage mode not active 1 = constant-voltage mode is active 8 chg_active 0 battery charger status 0 = not charging 1 = charging 7:0 chg_time_el apsed [7:0] 0000_0000 battery charger elapsed time 00h = 0min 01h = 2min 02h = 4min 03h = 6min ... ffh = 510min register 404ah charger status register address bit label default description refer to r16460 (404ch) status led 1 15:14 led1_src [1:0] 11 led1 source (selects the led1 function.) 00 = off 01 = power state status 10 = charger status 11 = manual mode note - led1 also indicates completion of otp auto program 9:8 led1_mode [1:0] 00 led1 mode (controls led1 in manual mode only.) 00 = off 01 = constant 10 = continuous pulsed 11 = pulsed sequence 5:4 led1_seq_le n [1:0] 10 led1 pulse sequence length (when led1_mode = pulsed sequence) 00 = 1 pulse 01 = 2 pulses 10 = 4 pulses 11 = 7 pulses 3:2 led1_dur [1:0] 01 led1 on time (when led1_mode = continuous pulsed or pulsed sequence) 00 = 1 second 01 = 250ms 10 = 125ms 11 = 62.5ms 1:0 led1_duty_c yc [1:0] 10 led1 duty cycle (on:off ratio) (when led1_mode = continuous pulsed or pulsed sequence) 00 = 1:1 (50% on) 01 = 1:2 (33.3% on) 10 = 1:3 (25% on)
pre-production WM8310 w pp, may 2012, rev 3.1 215 register address bit label default description refer to 11 = 1:7 (12.5% on) register 404ch status led 1 register address bit label default description refer to r16461 (404dh) status led 2 15:14 led2_src [1:0] 11 led2 source (selects the led2 function.) 00 = off 01 = power state status 10 = charger status 11 = manual mode note - led2 also indicates an otp auto program error condition 9:8 led2_mode [1:0] 00 led2 mode (controls led2 in manual mode only.) 00 = off 01 = constant 10 = continuous pulsed 11 = pulsed sequence 5:4 led2_seq_le n [1:0] 10 led2 pulse sequence length (when led2_mode = pulsed sequence) 00 = 1 pulse 01 = 2 pulses 10 = 4 pulses 11 = 7 pulses 3:2 led2_dur [1:0] 01 led2 on time (when led2_mode = continuous pulsed or pulsed sequence) 00 = 1 second 01 = 250ms 10 = 125ms 11 = 62.5ms 1:0 led2_duty_c yc [1:0] 10 led2 duty cycle (on:off ratio) (when led2_mode = continuous pulsed or pulsed sequence) 00 = 1:1 (50% on) 01 = 1:2 (33.3% on) 10 = 1:3 (25% on) 11 = 1:7 (12.5% on) register 404dh status led 2 register address bit label default description refer to r16462 (404eh) current sink 1 15 cs1_ena 0 current sink 1 enable (isink1 pin) 0 = disabled 1 = enabled note - this bit is reset to 0 when the off power state is entered. 14 cs1_drive 0 current sink 1 output drive enable 0 = disabled 1 = enabled 13 cs1_sts 0 current sink 1 status
WM8310 pre-production w pp, may 2012, rev 3.1 216 register address bit label default description refer to 0 = normal 1 = sink current cannot be regulated 12 cs1_slpena 0 current sink 1 sleep enable 0 = disabled 1 = controlled by cs1_ena 11:10 cs1_off_ra mp [1:0] 01 isink1 switch-off ramp 00 = instant (no ramp) 01 = 1 step every 4ms (220ms) 10 = 1 step every 8ms (440ms) 11 = 1 step every 16ms (880ms) the time quoted in brackets is valid for the maximum change in current drive setting. the actual time scales according to the extent of the change in current drive setting. 9:8 cs1_on_ram p [1:0] 01 isink1 switch-on ramp 00 = instant (no ramp) 01 = 1 step every 4ms (220ms) 10 = 1 step every 8ms (440ms) 11 = 1 step every 16ms (880ms) the time quoted in brackets is valid for the maximum change in current drive setting. the actual time scales according to the extent of the change in current drive setting. 5:0 cs1_isel [5:0] 00_0000 isink1 current. current = 2.0a 2^(cs1_isel/4), where cs1_isel is an unsigned binary number. alternatively, cs1_isel = 13.29 x log(current/2.0a) 00_0000 = 2.0a 11_0111 = 27.6ma values greater than 11_0111 will result in the maximum current of approx 27.6ma. register 404eh current sink 1 register address bit label default description refer to r16463 (404fh) current sink 2 15 cs2_ena 0 current sink 2 enable (isink2 pin) 0 = disabled 1 = enabled note - this bit is reset to 0 when the off power state is entered. 14 cs2_drive 0 current sink 2 output drive enable 0 = disabled 1 = enabled 13 cs2_sts 0 current sink 2 status 0 = normal 1 = sink current cannot be regulated 12 cs2_slpena 0 current sink 2 sleep enable 0 = disabled 1 = controlled by cs2_ena
pre-production WM8310 w pp, may 2012, rev 3.1 217 register address bit label default description refer to 11:10 cs2_off_ra mp [1:0] 01 isink2 switch-off ramp 00 = instant (no ramp) 01 = 1 step every 4ms (220ms) 10 = 1 step every 8ms (440ms) 11 = 1 step every 16ms (880ms) the time quoted in brackets is valid for the maximum change in current drive setting. the actual time scales according to the extent of the change in current drive setting. 9:8 cs2_on_ram p [1:0] 01 isink2 switch-on ramp 00 = instant (no ramp) 01 = 1 step every 4ms (220ms) 10 = 1 step every 8ms (440ms) 11 = 1 step every 16ms (880ms) the time quoted in brackets is valid for the maximum change in current drive setting. the actual time scales according to the extent of the change in current drive setting. 5:0 cs2_isel [5:0] 00_0000 isink2 current. current = 2.0a 2^(cs2_isel/4), where cs2_isel is an unsigned binary number. alternatively, cs2_isel = 13.29 x log(current/2.0a) 00_0000 = 2.0a 11_0111 = 27.6ma values greater than 11_0111 will result in the maximum current of approx 27.6ma. register 404fh current sink 2 register address bit label default description refer to r16464 (4050h) dcdc enable 7 epe2_ena 0 epe2 enable request 0 = disabled 1 = enabled (note that the actual status is indicated in epe2_sts) 6 epe1_ena 0 epe1 enable request 0 = disabled 1 = enabled (note that the actual status is indicated in epe1_sts) 3 dc4_ena 0 dc-dc4 enable request 0 = disabled 1 = enabled (note that the actual status is indicated in dc4_sts) 2 dc3_ena 0 dc-dc3 enable request 0 = disabled 1 = enabled (note that the actual status is indicated in dc3_sts) 1 dc2_ena 0 dc-dc2 enable request 0 = disabled 1 = enabled (note that the actual status is indicated in dc2_sts)
WM8310 pre-production w pp, may 2012, rev 3.1 218 register address bit label default description refer to 0 dc1_ena 0 dc_dc1 enable request 0 = disabled 1 = enabled (note that the actual status is indicated in dc1_sts) register 4050h dcdc enable register address bit label default description refer to r16465 (4051h) ldo enable 10 ldo11_ena 0 ldo11 enable request 0 = disabled 1 = enabled (note that the actual status is indicated in ldo11_sts) 9 ldo10_ena 0 ldo10 enable request 0 = disabled 1 = enabled (note that the actual status is indicated in ldo10_sts) 8 ldo9_ena 0 ldo9 enable request 0 = disabled 1 = enabled (note that the actual status is indicated in ldo9_sts) 7 ldo8_ena 0 ldo8 enable request 0 = disabled 1 = enabled (note that the actual status is indicated in ldo8_sts) 6 ldo7_ena 0 ldo7 enable request 0 = disabled 1 = enabled (note that the actual status is indicated in ldo7_sts) 5 ldo6_ena 0 ldo6 enable request 0 = disabled 1 = enabled (note that the actual status is indicated in ldo6_sts) 4 ldo5_ena 0 ldo5 enable request 0 = disabled 1 = enabled (note that the actual status is indicated in ldo5_sts) 3 ldo4_ena 0 ldo4 enable request 0 = disabled 1 = enabled (note that the actual status is indicated in ldo4_sts) 2 ldo3_ena 0 ldo3 enable request 0 = disabled 1 = enabled (note that the actual status is indicated in ldo3_sts) 1 ldo2_ena 0 ldo2 enable request 0 = disabled 1 = enabled (note that the actual status is indicated in ldo2_sts)
pre-production WM8310 w pp, may 2012, rev 3.1 219 register address bit label default description refer to 0 ldo1_ena 0 ldo1 enable request 0 = disabled 1 = enabled (note that the actual status is indicated in ldo1_sts) register 4051h ldo enable register address bit label default description refer to r16466 (4052h) dcdc status 7 epe2_sts 0 epe2 status 0 = disabled 1 = enabled 6 epe1_sts 0 epe1 status 0 = disabled 1 = enabled 3 dc4_sts 0 dc-dc4 status 0 = disabled 1 = enabled 2 dc3_sts 0 dc-dc3 status 0 = disabled 1 = enabled 1 dc2_sts 0 dc-dc2 status 0 = disabled 1 = enabled 0 dc1_sts 0 dc-dc1 status 0 = disabled 1 = enabled register 4052h dcdc status register address bit label default description refer to r16467 (4053h) ldo status 10 ldo11_sts 0 ldo11 status 0 = disabled 1 = enabled 9 ldo10_sts 0 ldo10 status 0 = disabled 1 = enabled 8 ldo9_sts 0 ldo9 status 0 = disabled 1 = enabled 7 ldo8_sts 0 ldo8 status 0 = disabled 1 = enabled 6 ldo7_sts 0 ldo7 status 0 = disabled 1 = enabled 5 ldo6_sts 0 ldo6 status 0 = disabled 1 = enabled
WM8310 pre-production w pp, may 2012, rev 3.1 220 register address bit label default description refer to 4 ldo5_sts 0 ldo5 status 0 = disabled 1 = enabled 3 ldo4_sts 0 ldo4 status 0 = disabled 1 = enabled 2 ldo3_sts 0 ldo3 status 0 = disabled 1 = enabled 1 ldo2_sts 0 ldo2 status 0 = disabled 1 = enabled 0 ldo1_sts 0 ldo1 status 0 = disabled 1 = enabled register 4053h ldo status register address bit label default description refer to r16468 (4054h) dcdc uv status 13 dc2_ov_sts 0 dc-dc2 overvoltage status 0 = normal 1 = overvoltage 12 dc1_ov_sts 0 dc-dc1 overvoltage status 0 = normal 1 = overvoltage 9 dc2_hc_sts 0 dc-dc2 high current status 0 = normal 1 = high current 8 dc1_hc_sts 0 dc-dc1 high current status 0 = normal 1 = high current 3 dc4_uv_sts 0 dc-dc4 undervoltage status 0 = normal 1 = undervoltage 2 dc3_uv_sts 0 dc-dc3 undervoltage status 0 = normal 1 = undervoltage 1 dc2_uv_sts 0 dc-dc2 undervoltage status 0 = normal 1 = undervoltage 0 dc1_uv_sts 0 dc-dc1 undervoltage status 0 = normal 1 = undervoltage register 4054h dcdc uv status
pre-production WM8310 w pp, may 2012, rev 3.1 221 register address bit label default description refer to r16469 (4055h) ldo uv status 15 intldo_uv_s ts 0 ldo13 (internal ldo) undervoltage status 0 = normal 1 = undervoltage 9 ldo10_uv_st s 0 ldo10 undervoltage status 0 = normal 1 = undervoltage 8 ldo9_uv_st s 0 ldo9 undervoltage status 0 = normal 1 = undervoltage 7 ldo8_uv_st s 0 ldo8 undervoltage status 0 = normal 1 = undervoltage 6 ldo7_uv_st s 0 ldo7 undervoltage status 0 = normal 1 = undervoltage 5 ldo6_uv_st s 0 ldo6 undervoltage status 0 = normal 1 = undervoltage 4 ldo5_uv_st s 0 ldo5 undervoltage status 0 = normal 1 = undervoltage 3 ldo4_uv_st s 0 ldo4 undervoltage status 0 = normal 1 = undervoltage 2 ldo3_uv_st s 0 ldo3 undervoltage status 0 = normal 1 = undervoltage 1 ldo2_uv_st s 0 ldo2 undervoltage status 0 = normal 1 = undervoltage 0 ldo1_uv_st s 0 ldo1 undervoltage status 0 = normal 1 = undervoltage register 4055h ldo uv status register address bit label default description refer to r16470 (4056h) dc1 control 1 15:14 dc1_rate [1:0] 10 dc-dc1 voltage ramp rate 00 = 1 step every 32us 01 = 1 step every 16us 10 = 1 step every 8us 11 = immediate voltage change 12 dc1_phase 0 dc-dc1 clock phase control 0 = normal 1 = inverted 9:8 dc1_freq [1:0] 00 dc-dc1 switching frequency 00 = reserved 01 = 2.0mhz 10 = reserved 11 = 4.0mhz
WM8310 pre-production w pp, may 2012, rev 3.1 222 register address bit label default description refer to 7 dc1_flt 0 dc-dc1 output float 0 = dc-dc1 output discharged when disabled 1 = dc-dc1 output floating when disabled 5:4 dc1_soft_st art [1:0] 00 dc-dc1 soft-start control (duration in each of the 8 startup current limiting steps.) 00 = 32us steps 01 = 64us steps 10 = 128us steps 11 = 256us steps 1:0 dc1_cap [1:0] 00 dc-dc1 output capacitor 00 = 4.7uf to 20uf 01 = reserved 10 = 22uf to 47uf 11 = reserved register 4056h dc1 control 1 register address bit label default description refer to r16471 (4057h) dc1 control 2 15:14 dc1_err_ac t [1:0] 00 dc-dc1 error action (undervoltage) 00 = ignore 01 = shut down converter 10 = shut down system (device reset) 11 = reserved note that an interrupt is always raised. 12:11 dc1_hwc_sr c [1:0] 00 dc-dc1 hardware control source 00 = disabled 01 = hardware control 1 10 = hardware control 2 11 = hardware control 1 or 2 10 dc1_hwc_vs el 0 dc-dc1 hardware control voltage select 0 = set by dc1_on_vsel 1 = set by dc1_slp_vsel 9:8 dc1_hwc_m ode [1:0] 11 dc-dc1 hardware control operating mode 00 = forced continuous conduction mode 01 = disabled 10 = ldo mode 11 = hysteretic mode 6:4 dc1_hc_thr [2:0] 000 dc-dc1 high current threshold 000 = 125ma 001 = 250ma 010 = 375ma 011 = 500ma 100 = 625ma 101 = 750ma 110 = 875ma 111 = 1000ma 0 dc1_hc_ind_ ena 0 dc-dc1 high current detect enable 0 = disabled 1 = enabled register 4057h dc1 control 2
pre-production WM8310 w pp, may 2012, rev 3.1 223 register address bit label default description refer to r16472 (4058h) dc1 on config 15:13 dc1_on_slo t [2:0] 000 dc-dc1 on slot select 000 = do not enable 001 = enable in timeslot 1 010 = enable in timeslot 2 011 = enable in timeslot 3 100 = enable in timeslot 4 101 = enable in timeslot 5 110 = controlled by hardware enable 1 111 = controlled by hardware enable 2 9:8 dc1_on_mod e [1:0] 01 dc-dc1 on operating mode 00 = forced continuous conduction mode 01 = auto mode (continuous / discontinuous conduction with pulse-skipping) 10 = ldo mode 11 = hysteretic mode 6:2 dc1_on_vse l [6:2] 0_0000 dc-dc1 on voltage select dc1_on_vsel [6:0] selects the dc-dc1 output voltage from 0.6v to 1.8v in 12.5mv steps. dc1_on_vsel [6:2] also exist in ice/otp memory, controlling the voltage in 50mv steps. dc1_on_vsel [6:0] is coded as follows: 00h to 08h = 0.6v 09h = 0.6125v ? 48h = 1.4v (see note) ? 67h = 1.7875v 68h to 7fh = 1.8v note - maximum output voltage selection in 4mhz switching mode is 48h (1.4v). 1:0 dc1_on_vse l [1:0] 00 dc-dc1 on voltage select dc1_on_vsel [6:0] selects the dc-dc1 output voltage from 0.6v to 1.8v in 12.5mv steps. see dc1_on_vsel [6:2] for definition. register 4058h dc1 on config register address bit label default description refer to r16473 (4059h) dc1 sleep control 15:13 dc1_slp_slo t [2:0] 000 dc-dc1 sleep slot select 000 = sleep voltage / operating mode transition in timeslot 5 001 = disable in timeslot 5 010 = disable in timeslot 4 011 = disable in timeslot 3 100 = disable in timeslot 2 101 = disable in timeslot 1 110 = sleep voltage / operating mode transition in timeslot 3 111 = sleep voltage / operating mode transition in timeslot 1
WM8310 pre-production w pp, may 2012, rev 3.1 224 register address bit label default description refer to if dc-dc1 is assigned to a hardware enable input, then codes 001-101 select in which timeslot the converter enters its sleep condition. 9:8 dc1_slp_mo de [1:0] 11 dc-dc1 sleep operating mode 00 = forced continuous conduction mode 01 = auto mode (continuous / discontinuous conduction with pulse-skipping) 10 = ldo mode 11 = hysteretic mode 6:0 dc1_slp_vse l [6:0] 000_0000 dc-dc1 sleep voltage select 0.6v to 1.8v in 12.5mv steps 00h to 08h = 0.6v 09h = 0.6125v ? 48h = 1.4v (see note) ? 67h = 1.7875v 68h to 7fh = 1.8v note - maximum output voltage selection in 4mhz switching mode is 48h (1.4v). register 4059h dc1 sleep control register address bit label default description refer to r16474 (405ah) dc1 dvs control 12:11 dc1_dvs_sr c [1:0] 00 dc-dc1 dvs control source 00 = disabled 01 = enabled 10 = controlled by hardware dvs1 11 = controlled by hardware dvs2 6:0 dc1_dvs_vs el [6:0] 000_0000 dc-dc1 dvs voltage select 0.6v to 1.8v in 12.5mv steps 00h to 08h = 0.6v 09h = 0.6125v ? 48h = 1.4v (see note) ? 67h = 1.7875v 68h to 7fh = 1.8v note - maximum output voltage selection in 4mhz switching mode is 48h (1.4v). register 405ah dc1 dvs control
pre-production WM8310 w pp, may 2012, rev 3.1 225 register address bit label default description refer to r16475 (405bh) dc2 control 1 15:14 dc2_rate [1:0] 10 dc-dc2 voltage ramp rate 00 = 1 step every 32us 01 = 1 step every 16us 10 = 1 step every 8us 11 = immediate voltage change 12 dc2_phase 1 dc-dc2 clock phase control 0 = normal 1 = inverted 9:8 dc2_freq [1:0] 00 dc-dc2 switching frequency 00 = reserved 01 = 2.0mhz 10 = reserved 11 = 4.0mhz 7 dc2_flt 0 dc-dc2 output float 0 = dc-dc2 output discharged when disabled 1 = dc-dc2 output floating when disabled 5:4 dc2_soft_st art [1:0] 00 dc-dc2 soft-start control (duration in each of the 8 startup current limiting steps.) 00 = 32us steps 01 = 64us steps 10 = 128us steps 11 = 256us steps 1:0 dc2_cap [1:0] 00 dc-dc2 output capacitor 00 = 4.7uf to 20uf 01 = reserved 10 = 22uf to 47uf 11 = reserved register 405bh dc2 control 1 register address bit label default description refer to r16476 (405ch) dc2 control 2 15:14 dc2_err_ac t [1:0] 00 dc-dc2 error action (undervoltage) 00 = ignore 01 = shut down converter 10 = shut down system (device reset) 11 = reserved note that an interrupt is always raised. 12:11 dc2_hwc_sr c [1:0] 00 dc-dc2 hardware control source 00 = disabled 01 = hardware control 1 10 = hardware control 2 11 = hardware control 1 or 2 10 dc2_hwc_vs el 0 dc-dc2 hardware control voltage select 0 = set by dc2_on_vsel 1 = set by dc2_slp_vsel 9:8 dc2_hwc_m ode [1:0] 11 dc-dc2 hardware control operating mode 00 = forced continuous conduction mode 01 = disabled 10 = ldo mode 11 = hysteretic mode
WM8310 pre-production w pp, may 2012, rev 3.1 226 register address bit label default description refer to 6:4 dc2_hc_thr [2:0] 000 dc-dc2 high current threshold 000 = 125ma 001 = 250ma 010 = 375ma 011 = 500ma 100 = 625ma 101 = 750ma 110 = 875ma 111 = 1000ma 0 dc2_hc_ind_ ena 0 dc-dc2 high current detect enable 0 = disabled 1 = enabled register 405ch dc2 control 2 register address bit label default description refer to r16477 (405dh) dc2 on config 15:13 dc2_on_slo t [2:0] 000 dc-dc2 on slot select 000 = do not enable 001 = enable in timeslot 1 010 = enable in timeslot 2 011 = enable in timeslot 3 100 = enable in timeslot 4 101 = enable in timeslot 5 110 = controlled by hardware enable 1 111 = controlled by hardware enable 2 9:8 dc2_on_mod e [1:0] 01 dc-dc2 on operating mode 00 = forced continuous conduction mode 01 = auto mode (continuous / discontinuous conduction with pulse-skipping) 10 = ldo mode 11 = hysteretic mode 6:2 dc2_on_vse l [6:2] 0_0000 dc-dc2 on voltage select dc2_on_vsel [6:0] selects the dc-dc2 output voltage from 0.6v to 1.8v in 12.5mv steps. dc2_on_vsel [6:2] also exist in ice/otp memory, controlling the voltage in 50mv steps. dc2_on_vsel [6:0] is coded as follows: 00h to 08h = 0.6v 09h = 0.6125v ? 48h = 1.4v (see note) ? 67h = 1.7875v 68h to 7fh = 1.8v note - maximum output voltage selection in 4mhz switching mode is 48h (1.4v). 1:0 dc2_on_vse l [1:0] 00 dc-dc2 on voltage select dc2_on_vsel [6:0] selects the dc-dc2 output voltage from 0.6v to 1.8v in 12.5mv steps. see dc2_on_vsel [6:2] for definition. register 405dh dc2 on config
pre-production WM8310 w pp, may 2012, rev 3.1 227 register address bit label default description refer to r16478 (405eh) dc2 sleep control 15:13 dc2_slp_slo t [2:0] 000 dc-dc2 sleep slot select 000 = sleep voltage / operating mode transition in timeslot 5 001 = disable in timeslot 5 010 = disable in timeslot 4 011 = disable in timeslot 3 100 = disable in timeslot 2 101 = disable in timeslot 1 110 = sleep voltage / operating mode transition in timeslot 3 111 = sleep voltage / operating mode transition in timeslot 1 if dc-dc2 is assigned to a hardware enable input, then codes 001-101 select in which timeslot the converter enters its sleep condition. 9:8 dc2_slp_mo de [1:0] 11 dc-dc2 sleep operating mode 00 = forced continuous conduction mode 01 = auto mode (continuous / discontinuous conduction with pulse-skipping) 10 = ldo mode 11 = hysteretic mode 6:0 dc2_slp_vse l [6:0] 000_0000 dc-dc2 sleep voltage select 0.6v to 1.8v in 12.5mv steps 00h to 08h = 0.6v 09h = 0.6125v ? 48h = 1.4v (see note) ? 67h = 1.7875v 68h to 7fh = 1.8v note - maximum output voltage selection in 4mhz switching mode is 48h (1.4v). register 405eh dc2 sleep control register address bit label default description refer to r16479 (405fh) dc2 dvs control 12:11 dc2_dvs_sr c [1:0] 00 dc-dc2 dvs control source 00 = disabled 01 = enabled 10 = controlled by hardware dvs1 11 = controlled by hardware dvs2 6:0 dc2_dvs_vs el [6:0] 000_0000 dc-dc2 dvs voltage select 0.6v to 1.8v in 12.5mv steps 00h to 08h = 0.6v 09h = 0.6125v ? 48h = 1.4v (see note) ? 67h = 1.7875v
WM8310 pre-production w pp, may 2012, rev 3.1 228 register address bit label default description refer to 68h to 7fh = 1.8v note - maximum output voltage selection in 4mhz switching mode is 48h (1.4v). register 405fh dc2 dvs control register address bit label default description refer to r16480 (4060h) dc3 control 1 12 dc3_phase 0 dc-dc3 clock phase control 0 = normal 1 = inverted 7 dc3_flt 0 dc-dc3 output float 0 = dc-dc3 output discharged when disabled 1 = dc-dc3 output floating when disabled 5:4 dc3_soft_st art [1:0] 01 dc-dc3 soft-start control (duration in each of the 3 intermediate startup current limiting steps.) 00 = immediate start-up 01 = 512us steps 10 = 4.096ms steps 11 = 32.768ms steps 3:2 dc3_stnby_l im [1:0] 01 dc-dc3 current limit sets the maximum dc output current in hysteretic mode. typical values shown below. 00 = 100ma 01 = 200ma 10 = 400ma 11 = 800ma protected by security key. 1:0 dc3_cap [1:0] 00 dc-dc3 output capacitor 00 = 10uf to 20uf 01 = 10uf to 20uf 10 = 22uf to 45uf 11 = 47uf to 100uf register 4060h dc3 control 1 register address bit label default description refer to r16481 (4061h) dc3 control 2 15:14 dc3_err_ac t [1:0] 00 dc-dc3 error action (undervoltage) 00 = ignore 01 = shut down converter 10 = shut down system (device reset) 11 = reserved note that an interrupt is always raised. 12:11 dc3_hwc_sr c [1:0] 00 dc-dc3 hardware control source 00 = disabled 01 = hardware control 1 10 = hardware control 2 11 = hardware control 1 or 2 10 dc3_hwc_vs el 0 dc-dc3 hardware control voltage select 0 = set by dc3_on_vsel 1 = set by dc3_slp_vsel
pre-production WM8310 w pp, may 2012, rev 3.1 229 register address bit label default description refer to 9:8 dc3_hwc_m ode [1:0] 11 dc-dc3 hardware control operating mode 00 = forced continuous conduction mode 01 = disabled 10 = ldo mode 11 = hysteretic mode 7 dc3_ovp 0 dc-dc3 overvoltage protection 0 = disabled 1 = enabled register 4061h dc3 control 2 register address bit label default description refer to r16482 (4062h) dc3 on config 15:13 dc3_on_slo t [2:0] 000 dc-dc3 on slot select 000 = do not enable 001 = enable in timeslot 1 010 = enable in timeslot 2 011 = enable in timeslot 3 100 = enable in timeslot 4 101 = enable in timeslot 5 110 = controlled by hardware enable 1 111 = controlled by hardware enable 2 9:8 dc3_on_mod e [1:0] 01 dc-dc3 on operating mode 00 = forced continuous conduction mode 01 = auto mode (continuous / discontinuous conduction with pulse-skipping) 10 = ldo mode 11 = hysteretic mode 6:2 dc3_on_vse l [6:2] 0_0000 dc-dc3 on voltage select dc3_on_vsel [6:0] selects the dc-dc3 output voltage from 0.85v to 3.4v in 25mv steps. dc3_on_vsel [6:2] also exist in ice/otp memory, controlling the voltage in 100mv steps. dc3_on_vsel [6:0] is coded as follows: 00h = 0.85v 01h = 0.875v ? 65h = 3.375v 66h to 7fh = 3.4v 1:0 dc3_on_vse l [1:0] 00 dc3 on voltage select dc3_on_vsel [6:0] selects the dc3 output voltage from 0.85v to 3.4v in 25mv steps. see dc3_on_vsel [6:2] for definition. register 4062h dc3 on config
WM8310 pre-production w pp, may 2012, rev 3.1 230 register address bit label default description refer to r16483 (4063h) dc3 sleep control 15:13 dc3_slp_slo t [2:0] 000 dc-dc3 sleep slot select 000 = sleep voltage / operating mode transition in timeslot 5 001 = disable in timeslot 5 010 = disable in timeslot 4 011 = disable in timeslot 3 100 = disable in timeslot 2 101 = disable in timeslot 1 110 = sleep voltage / operating mode transition in timeslot 3 111 = sleep voltage / operating mode transition in timeslot 1 if dc-dc3 is assigned to a hardware enable input, then codes 001-101 select in which timeslot the converter enters its sleep condition. 9:8 dc3_slp_mo de [1:0] 11 dc-dc3 sleep operating mode 00 = forced continuous conduction mode 01 = auto mode (continuous / discontinuous conduction with pulse-skipping) 10 = ldo mode 11 = hysteretic mode 6:0 dc3_slp_vse l [6:0] 000_0000 dc-dc3 sleep voltage select 0.85v to 3.4v in 25mv steps 00h = 0.85v 01h = 0.875v ? 65h = 3.375v 66h to 7fh = 3.4v register 4063h dc3 sleep control register address bit label default description refer to r16484 (4064h) dc4 control 15:14 dc4_err_ac t [1:0] 00 dc-dc4 error action (undervoltage) 00 = ignore 01 = shut down converter 10 = shut down system (device reset) 11 = reserved note that an interrupt is always raised. 12:11 dc4_hwc_sr c [1:0] 00 dc-dc4 hardware control source 00 = disabled 01 = hardware control 1 10 = hardware control 2 11 = hardware control 1 or 2 8 dc4_hwc_m ode 1 dc-dc4 hardware control operating mode 0 = dc-dc4 is controlled by dc4_ena 1 = dc-dc4 is disabled when hardware control source is asserted 3:2 dc4_range [1:0] 01 selects the voltage range for dc-dc4 00 = 20v < vout <= 30v 01 = 10v < vout <= 20v 10 = 6.5v < vout <= 10v
pre-production WM8310 w pp, may 2012, rev 3.1 231 register address bit label default description refer to 11 = reserved protected by security key. 0 dc4_fbsrc 0 dc-dc4 voltage feedback source 0 = isink1 1 = isink2 register 4064h dc4 control register address bit label default description refer to r16485 (4065h) dc4 sleep control 8 dc4_slpena 0 dc-dc4 sleep enable 0 = disabled 1 = controlled by dc4_ena register 4065h dc4 sleep control register address bit label default description refer to r16486 (4066h) epe1 control 15:13 epe1_on_sl ot [2:0] 000 epe1 on slot select 000 = do not enable 001 = enable in timeslot 1 010 = enable in timeslot 2 011 = enable in timeslot 3 100 = enable in timeslot 4 101 = enable in timeslot 5 110 = controlled by hardware enable 1 111 = controlled by hardware enable 2 12:11 epe1_hwc_s rc [1:0] 00 epe1 hardware control source 00 = disabled 01 = hardware control 1 10 = hardware control 2 11 = hardware control 1 or 2 8 epe1_hwcen a 0 epe1 hardware control enable 0 = epe1 is controlled by epe1_ena (hardware control input(s) are ignored) 1 = epe1 is controlled by hwc inputs (hardware control input(s) force epe1 to be de-asserted) 7:5 epe1_slp_sl ot [2:0] 000 epe1 sleep slot select 000 = no action 001 = disable in timeslot 5 010 = disable in timeslot 4 011 = disable in timeslot 3 100 = disable in timeslot 2 101 = disable in timeslot 1 110 = no action 111 = no action register 4066h epe1 control
WM8310 pre-production w pp, may 2012, rev 3.1 232 register address bit label default description refer to r16487 (4067h) epe2 control 15:13 epe2_on_sl ot [2:0] 000 epe2 on slot select 000 = do not enable 001 = enable in timeslot 1 010 = enable in timeslot 2 011 = enable in timeslot 3 100 = enable in timeslot 4 101 = enable in timeslot 5 110 = controlled by hardware enable 1 111 = controlled by hardware enable 2 12:11 epe2_hwc_s rc [1:0] 00 epe2 hardware control source 00 = disabled 01 = hardware control 1 10 = hardware control 2 11 = hardware control 1 or 2 8 epe2_hwcen a 0 epe2 hardware control enable 0 = epe2 is controlled by epe2_ena (hardware control input(s) are ignored) 1 = epe2 is controlled by hwc inputs (hardware control input(s) force epe2 to be de-asserted) 7:5 epe2_slp_sl ot [2:0] 000 epe2 sleep slot select 000 = no action 001 = disable in timeslot 5 010 = disable in timeslot 4 011 = disable in timeslot 3 100 = disable in timeslot 2 101 = disable in timeslot 1 110 = no action 111 = no action register 4067h epe2 control register address bit label default description refer to r16488 (4068h) ldo1 control 15:14 ldo1_err_a ct [1:0] 00 ldo1 error action (undervoltage) 00 = ignore 01 = shut down regulator 10 = shut down system (device reset) 11 = reserved note that an interrupt is always raised. 12:11 ldo1_hwc_s rc [1:0] 00 ldo1 hardware control source 00 = disabled 01 = hardware control 1 10 = hardware control 2 11 = hardware control 1 or 2 10 ldo1_hwc_v sel 0 ldo1 hardware control voltage select 0 = set by ldo1_on_vsel 1 = set by ldo1_slp_vsel 9:8 ldo1_hwc_m ode [1:0] 10 ldo1 hardware control operating mode 00 = low power mode 01 = turn converter off 10 = low power mode 11 = set by ldo1_on_mode
pre-production WM8310 w pp, may 2012, rev 3.1 233 register address bit label default description refer to 7 ldo1_flt 0 ldo1 output float 0 = ldo1 output discharged when disabled 1 = ldo1 output floating when disabled 6 ldo1_swi 0 ldo1 switch mode 0 = ldo mode 1 = switch mode 0 ldo1_lp_mo de 0 ldo1 low power mode select 0 = 50ma (reduced quiescent current) 1 = 20ma (minimum quiescent current) selects which low power mode is used in on, sleep, or under hwc modes. register 4068h ldo1 control register address bit label default description refer to r16489 (4069h) ldo1 on control 15:13 ldo1_on_sl ot [2:0] 000 ldo1 on slot select 000 = do not enable 001 = enable in timeslot 1 010 = enable in timeslot 2 011 = enable in timeslot 3 100 = enable in timeslot 4 101 = enable in timeslot 5 110 = controlled by hardware enable 1 111 = controlled by hardware enable 2 8 ldo1_on_mo de 0 ldo1 on operating mode 0 = normal mode 1 = low power mode 4:0 ldo1_on_vs el [4:0] 0_0000 ldo1 on voltage select 0.9v to 1.6v in 50mv steps 1.7v to 3.3v in 100mv steps 00h = 0.90v 01h = 0.95v ? 0eh = 1.60v 0fh = 1.70v ? 1eh = 3.20v 1fh = 3.30v register 4069h ldo1 on control
WM8310 pre-production w pp, may 2012, rev 3.1 234 register address bit label default description refer to r16490 (406ah) ldo1 sleep control 15:13 ldo1_slp_sl ot [2:0] 000 ldo1 sleep slot select 000 = sleep voltage / operating mode transition in timeslot 5 001 = disable in timeslot 5 010 = disable in timeslot 4 011 = disable in timeslot 3 100 = disable in timeslot 2 101 = disable in timeslot 1 110 = sleep voltage / operating mode transition in timeslot 3 111 = sleep voltage / operating mode transition in timeslot 1 if ldo1 is assigned to a hardware enable input, then codes 001-101 select in which timeslot the regulator enters its sleep condition. 8 ldo1_slp_m ode 1 ldo1 sleep operating mode 0 = normal mode 1 = low power mode 4:0 ldo1_slp_vs el [4:0] 0_0000 ldo1 sleep voltage select 0.9v to 1.6v in 50mv steps 1.7v to 3.3v in 100mv steps 00h = 0.90v 01h = 0.95v ? 0eh = 1.60v 0fh = 1.70v ? 1eh = 3.20v 1fh = 3.30v register 406ah ldo1 sleep control register address bit label default description refer to r16491 (406bh) ldo2 control 15:14 ldo2_err_a ct [1:0] 00 ldo2 error action (undervoltage) 00 = ignore 01 = shut down regulator 10 = shut down system (device reset) 11 = reserved note that an interrupt is always raised. 12:11 ldo2_hwc_s rc [1:0] 00 ldo2 hardware control source 00 = disabled 01 = hardware control 1 10 = hardware control 2 11 = hardware control 1 or 2 10 ldo2_hwc_v sel 0 ldo2 hardware control voltage select 0 = set by ldo2_on_vsel 1 = set by ldo2_slp_vsel 9:8 ldo2_hwc_m ode [1:0] 10 ldo2 hardware control operating mode 00 = low power mode 01 = turn converter off 10 = low power mode
pre-production WM8310 w pp, may 2012, rev 3.1 235 register address bit label default description refer to 11 = set by ldo2_on_mode 7 ldo2_flt 0 ldo2 output float 0 = ldo2 output discharged when disabled 1 = ldo2 output floating when disabled 6 ldo2_swi 0 ldo2 switch mode 0 = ldo mode 1 = switch mode 0 ldo2_lp_mo de 0 ldo2 low power mode select 0 = 50ma (reduced quiescent current) 1 = 20ma (minimum quiescent current) selects which low power mode is used in on, sleep, or under hwc modes. register 406bh ldo2 control register address bit label default description refer to r16492 (406ch) ldo2 on control 15:13 ldo2_on_sl ot [2:0] 000 ldo2 on slot select 000 = do not enable 001 = enable in timeslot 1 010 = enable in timeslot 2 011 = enable in timeslot 3 100 = enable in timeslot 4 101 = enable in timeslot 5 110 = controlled by hardware enable 1 111 = controlled by hardware enable 2 8 ldo2_on_mo de 0 ldo2 on operating mode 0 = normal mode 1 = low power mode 4:0 ldo2_on_vs el [4:0] 0_0000 ldo2 on voltage select 0.9v to 1.6v in 50mv steps 1.7v to 3.3v in 100mv steps 00h = 0.90v 01h = 0.95v ? 0eh = 1.60v 0fh = 1.70v ? 1eh = 3.20v 1fh = 3.30v register 406ch ldo2 on control
WM8310 pre-production w pp, may 2012, rev 3.1 236 register address bit label default description refer to r16493 (406dh) ldo2 sleep control 15:13 ldo2_slp_sl ot [2:0] 000 ldo2 sleep slot select 000 = sleep voltage / operating mode transition in timeslot 5 001 = disable in timeslot 5 010 = disable in timeslot 4 011 = disable in timeslot 3 100 = disable in timeslot 2 101 = disable in timeslot 1 110 = sleep voltage / operating mode transition in timeslot 3 111 = sleep voltage / operating mode transition in timeslot 1 if ldo2 is assigned to a hardware enable input, then codes 001-101 select in which timeslot the regulator enters its sleep condition. 8 ldo2_slp_m ode 1 ldo2 sleep operating mode 0 = normal mode 1 = low power mode 4:0 ldo2_slp_vs el [4:0] 0_0000 ldo2 sleep voltage select 0.9v to 1.6v in 50mv steps 1.7v to 3.3v in 100mv steps 00h = 0.90v 01h = 0.95v ? 0eh = 1.60v 0fh = 1.70v ? 1eh = 3.20v 1fh = 3.30v register 406dh ldo2 sleep control register address bit label default description refer to r16494 (406eh) ldo3 control 15:14 ldo3_err_a ct [1:0] 00 ldo3 error action (undervoltage) 00 = ignore 01 = shut down regulator 10 = shut down system (device reset) 11 = reserved note that an interrupt is always raised. 12:11 ldo3_hwc_s rc [1:0] 00 ldo3 hardware control source 00 = disabled 01 = hardware control 1 10 = hardware control 2 11 = hardware control 1 or 2 10 ldo3_hwc_v sel 0 ldo3 hardware control voltage select 0 = set by ldo3_on_vsel 1 = set by ldo3_slp_vsel
pre-production WM8310 w pp, may 2012, rev 3.1 237 register address bit label default description refer to 9:8 ldo3_hwc_m ode [1:0] 10 ldo3 hardware control operating mode 00 = low power mode 01 = turn converter off 10 = low power mode 11 = set by ldo3_on_mode 7 ldo3_flt 0 ldo3 output float 0 = ldo3 output discharged when disabled 1 = ldo3 output floating when disabled 6 ldo3_swi 0 ldo3 switch mode 0 = ldo mode 1 = switch mode 0 ldo3_lp_mo de 0 ldo3 low power mode select 0 = 50ma (reduced quiescent current) 1 = 20ma (minimum quiescent current) selects which low power mode is used in on, sleep, or under hwc modes. register 406eh ldo3 control register address bit label default description refer to r16495 (406fh) ldo3 on control 15:13 ldo3_on_sl ot [2:0] 000 ldo3 on slot select 000 = do not enable 001 = enable in timeslot 1 010 = enable in timeslot 2 011 = enable in timeslot 3 100 = enable in timeslot 4 101 = enable in timeslot 5 110 = controlled by hardware enable 1 111 = controlled by hardware enable 2 8 ldo3_on_mo de 0 ldo3 on operating mode 0 = normal mode 1 = low power mode 4:0 ldo3_on_vs el [4:0] 0_0000 ldo3 on voltage select 0.9v to 1.6v in 50mv steps 1.7v to 3.3v in 100mv steps 00h = 0.90v 01h = 0.95v ? 0eh = 1.60v 0fh = 1.70v ? 1eh = 3.20v 1fh = 3.30v register 406fh ldo3 on control
WM8310 pre-production w pp, may 2012, rev 3.1 238 register address bit label default description refer to r16496 (4070h) ldo3 sleep control 15:13 ldo3_slp_sl ot [2:0] 000 ldo3 sleep slot select 000 = sleep voltage / operating mode transition in timeslot 5 001 = disable in timeslot 5 010 = disable in timeslot 4 011 = disable in timeslot 3 100 = disable in timeslot 2 101 = disable in timeslot 1 110 = sleep voltage / operating mode transition in timeslot 3 111 = sleep voltage / operating mode transition in timeslot 1 if ldo3 is assigned to a hardware enable input, then codes 001-101 select in which timeslot the regulator enters its sleep condition. 8 ldo3_slp_m ode 1 ldo3 sleep operating mode 0 = normal mode 1 = low power mode 4:0 ldo3_slp_vs el [4:0] 0_0000 ldo3 sleep voltage select 0.9v to 1.6v in 50mv steps 1.7v to 3.3v in 100mv steps 00h = 0.90v 01h = 0.95v ? 0eh = 1.60v 0fh = 1.70v ? 1eh = 3.20v 1fh = 3.30v register 4070h ldo3 sleep control register address bit label default description refer to r16497 (4071h) ldo4 control 15:14 ldo4_err_a ct [1:0] 00 ldo4 error action (undervoltage) 00 = ignore 01 = shut down regulator 10 = shut down system (device reset) 11 = reserved note that an interrupt is always raised. 12:11 ldo4_hwc_s rc [1:0] 00 ldo4 hardware control source 00 = disabled 01 = hardware control 1 10 = hardware control 2 11 = hardware control 1 or 2 10 ldo4_hwc_v sel 0 ldo4 hardware control voltage select 0 = set by ldo4_on_vsel 1 = set by ldo4_slp_vsel
pre-production WM8310 w pp, may 2012, rev 3.1 239 register address bit label default description refer to 9:8 ldo4_hwc_m ode [1:0] 10 ldo4 hardware control operating mode 00 = low power mode 01 = turn converter off 10 = low power mode 11 = set by ldo4_on_mode 7 ldo4_flt 0 ldo4 output float 0 = ldo4 output discharged when disabled 1 = ldo4 output floating when disabled 6 ldo4_swi 0 ldo4 switch mode 0 = ldo mode 1 = switch mode 0 ldo4_lp_mo de 0 ldo4 low power mode select 0 = 50ma (reduced quiescent current) 1 = 20ma (minimum quiescent current) selects which low power mode is used in on, sleep, or under hwc modes. register 4071h ldo4 control register address bit label default description refer to r16498 (4072h) ldo4 on control 15:13 ldo4_on_sl ot [2:0] 000 ldo4 on slot select 000 = do not enable 001 = enable in timeslot 1 010 = enable in timeslot 2 011 = enable in timeslot 3 100 = enable in timeslot 4 101 = enable in timeslot 5 110 = controlled by hardware enable 1 111 = controlled by hardware enable 2 8 ldo4_on_mo de 0 ldo4 on operating mode 0 = normal mode 1 = low power mode 4:0 ldo4_on_vs el [4:0] 0_0000 ldo4 on voltage select 0.9v to 1.6v in 50mv steps 1.7v to 3.3v in 100mv steps 00h = 0.90v 01h = 0.95v ? 0eh = 1.60v 0fh = 1.70v ? 1eh = 3.20v 1fh = 3.30v register 4072h ldo4 on control
WM8310 pre-production w pp, may 2012, rev 3.1 240 register address bit label default description refer to r16499 (4073h) ldo4 sleep control 15:13 ldo4_slp_sl ot [2:0] 000 ldo4 sleep slot select 000 = sleep voltage / operating mode transition in timeslot 5 001 = disable in timeslot 5 010 = disable in timeslot 4 011 = disable in timeslot 3 100 = disable in timeslot 2 101 = disable in timeslot 1 110 = sleep voltage / operating mode transition in timeslot 3 111 = sleep voltage / operating mode transition in timeslot 1 if ldo4 is assigned to a hardware enable input, then codes 001-101 select in which timeslot the regulator enters its sleep condition. 8 ldo4_slp_m ode 1 ldo4 sleep operating mode 0 = normal mode 1 = low power mode 4:0 ldo4_slp_vs el [4:0] 0_0000 ldo4 sleep voltage select 0.9v to 1.6v in 50mv steps 1.7v to 3.3v in 100mv steps 00h = 0.90v 01h = 0.95v ? 0eh = 1.60v 0fh = 1.70v ? 1eh = 3.20v 1fh = 3.30v register 4073h ldo4 sleep control register address bit label default description refer to r16500 (4074h) ldo5 control 15:14 ldo5_err_a ct [1:0] 00 ldo5 error action (undervoltage) 00 = ignore 01 = shut down regulator 10 = shut down system (device reset) 11 = reserved note that an interrupt is always raised. 12:11 ldo5_hwc_s rc [1:0] 00 ldo5 hardware control source 00 = disabled 01 = hardware control 1 10 = hardware control 2 11 = hardware control 1 or 2 10 ldo5_hwc_v sel 0 ldo5 hardware control voltage select 0 = set by ldo5_on_vsel 1 = set by ldo5_slp_vsel
pre-production WM8310 w pp, may 2012, rev 3.1 241 register address bit label default description refer to 9:8 ldo5_hwc_m ode [1:0] 10 ldo5 hardware control operating mode 00 = low power mode 01 = turn converter off 10 = low power mode 11 = set by ldo5_on_mode 7 ldo5_flt 0 ldo5 output float 0 = ldo5 output discharged when disabled 1 = ldo5 output floating when disabled 6 ldo5_swi 0 ldo5 switch mode 0 = ldo mode 1 = switch mode 0 ldo5_lp_mo de 0 ldo5 low power mode select 0 = 50ma (reduced quiescent current) 1 = 20ma (minimum quiescent current) selects which low power mode is used in on, sleep, or under hwc modes. register 4074h ldo5 control register address bit label default description refer to r16501 (4075h) ldo5 on control 15:13 ldo5_on_sl ot [2:0] 000 ldo5 on slot select 000 = do not enable 001 = enable in timeslot 1 010 = enable in timeslot 2 011 = enable in timeslot 3 100 = enable in timeslot 4 101 = enable in timeslot 5 110 = controlled by hardware enable 1 111 = controlled by hardware enable 2 8 ldo5_on_mo de 0 ldo5 on operating mode 0 = normal mode 1 = low power mode 4:0 ldo5_on_vs el [4:0] 0_0000 ldo5 on voltage select 0.9v to 1.6v in 50mv steps 1.7v to 3.3v in 100mv steps 00h = 0.90v 01h = 0.95v ? 0eh = 1.60v 0fh = 1.70v ? 1eh = 3.20v 1fh = 3.30v register 4075h ldo5 on control
WM8310 pre-production w pp, may 2012, rev 3.1 242 register address bit label default description refer to r16502 (4076h) ldo5 sleep control 15:13 ldo5_slp_sl ot [2:0] 000 ldo5 sleep slot select 000 = sleep voltage / operating mode transition in timeslot 5 001 = disable in timeslot 5 010 = disable in timeslot 4 011 = disable in timeslot 3 100 = disable in timeslot 2 101 = disable in timeslot 1 110 = sleep voltage / operating mode transition in timeslot 3 111 = sleep voltage / operating mode transition in timeslot 1 if ldo5 is assigned to a hardware enable input, then codes 001-101 select in which timeslot the regulator enters its sleep condition. 8 ldo5_slp_m ode 1 ldo5 sleep operating mode 0 = normal mode 1 = low power mode 4:0 ldo5_slp_vs el [4:0] 0_0000 ldo5 sleep voltage select 0.9v to 1.6v in 50mv steps 1.7v to 3.3v in 100mv steps 00h = 0.90v 01h = 0.95v ? 0eh = 1.60v 0fh = 1.70v ? 1eh = 3.20v 1fh = 3.30v register 4076h ldo5 sleep control register address bit label default description refer to r16503 (4077h) ldo6 control 15:14 ldo6_err_a ct [1:0] 00 ldo6 error action (undervoltage) 00 = ignore 01 = shut down regulator 10 = shut down system (device reset) 11 = reserved note that an interrupt is always raised. 12:11 ldo6_hwc_s rc [1:0] 00 ldo6 hardware control source 00 = disabled 01 = hardware control 1 10 = hardware control 2 11 = hardware control 1 or 2 10 ldo6_hwc_v sel 0 ldo6 hardware control voltage select 0 = set by ldo6_on_vsel 1 = set by ldo6_slp_vsel
pre-production WM8310 w pp, may 2012, rev 3.1 243 register address bit label default description refer to 9:8 ldo6_hwc_m ode [1:0] 10 ldo6 hardware control operating mode 00 = low power mode 01 = turn converter off 10 = low power mode 11 = set by ldo6_on_mode 7 ldo6_flt 0 ldo6 output float 0 = ldo6 output discharged when disabled 1 = ldo6 output floating when disabled 6 ldo6_swi 0 ldo6 switch mode 0 = ldo mode 1 = switch mode 0 ldo6_lp_mo de 0 ldo6 low power mode select 0 = 50ma (reduced quiescent current) 1 = 20ma (minimum quiescent current) selects which low power mode is used in on, sleep, or under hwc modes. register 4077h ldo6 control register address bit label default description refer to r16504 (4078h) ldo6 on control 15:13 ldo6_on_sl ot [2:0] 000 ldo6 on slot select 000 = do not enable 001 = enable in timeslot 1 010 = enable in timeslot 2 011 = enable in timeslot 3 100 = enable in timeslot 4 101 = enable in timeslot 5 110 = controlled by hardware enable 1 111 = controlled by hardware enable 2 8 ldo6_on_mo de 0 ldo6 on operating mode 0 = normal mode 1 = low power mode 4:0 ldo6_on_vs el [4:0] 0_0000 ldo6 on voltage select 0.9v to 1.6v in 50mv steps 1.7v to 3.3v in 100mv steps 00h = 0.90v 01h = 0.95v ? 0eh = 1.60v 0fh = 1.70v ? 1eh = 3.20v 1fh = 3.30v register 4078h ldo6 on control
WM8310 pre-production w pp, may 2012, rev 3.1 244 register address bit label default description refer to r16505 (4079h) ldo6 sleep control 15:13 ldo6_slp_sl ot [2:0] 000 ldo6 sleep slot select 000 = sleep voltage / operating mode transition in timeslot 5 001 = disable in timeslot 5 010 = disable in timeslot 4 011 = disable in timeslot 3 100 = disable in timeslot 2 101 = disable in timeslot 1 110 = sleep voltage / operating mode transition in timeslot 3 111 = sleep voltage / operating mode transition in timeslot 1 if ldo6 is assigned to a hardware enable input, then codes 001-101 select in which timeslot the regulator enters its sleep condition. 8 ldo6_slp_m ode 1 ldo6 sleep operating mode 0 = normal mode 1 = low power mode 4:0 ldo6_slp_vs el [4:0] 0_0000 ldo6 sleep voltage select 0.9v to 1.6v in 50mv steps 1.7v to 3.3v in 100mv steps 00h = 0.90v 01h = 0.95v ? 0eh = 1.60v 0fh = 1.70v ? 1eh = 3.20v 1fh = 3.30v register 4079h ldo6 sleep control register address bit label default description refer to r16506 (407ah) ldo7 control 15:14 ldo7_err_a ct [1:0] 00 ldo7 error action (undervoltage) 00 = ignore 01 = shut down regulator 10 = shut down system (device reset) 11 = reserved note that an interrupt is always raised. 12:11 ldo7_hwc_s rc [1:0] 00 ldo7 hardware control source 00 = disabled 01 = hardware control 1 10 = hardware control 2 11 = hardware control 1 or 2 10 ldo7_hwc_v sel 0 ldo7 hardware control voltage select 0 = set by ldo7_on_vsel 1 = set by ldo7_slp_vsel
pre-production WM8310 w pp, may 2012, rev 3.1 245 register address bit label default description refer to 9:8 ldo7_hwc_m ode [1:0] 10 ldo7 hardware control operating mode 00 = low power mode 01 = turn converter off 10 = low power mode 11 = set by ldo7_on_mode 7 ldo7_flt 0 ldo7 output float 0 = ldo7 output discharged when disabled 1 = ldo7 output floating when disabled 6 ldo7_swi 0 ldo7 switch mode 0 = ldo mode 1 = switch mode register 407ah ldo7 control register address bit label default description refer to r16507 (407bh) ldo7 on control 15:13 ldo7_on_sl ot [2:0] 000 ldo7 on slot select 000 = do not enable 001 = enable in timeslot 1 010 = enable in timeslot 2 011 = enable in timeslot 3 100 = enable in timeslot 4 101 = enable in timeslot 5 110 = controlled by hardware enable 1 111 = controlled by hardware enable 2 8 ldo7_on_mo de 0 ldo7 on operating mode 0 = normal mode 1 = low power mode 4:0 ldo7_on_vs el [4:0] 0_0000 ldo7 on voltage select 1.0v to 1.6v in 50mv steps 1.7v to 3.5v in 100mv steps 00h = 1.00v 01h = 1.05v 02h = 1.10v ? 0ch = 1.60v 0dh = 1.70v ? 1eh = 3.40v 1fh = 3.50v register 407bh ldo7 on control register address bit label default description refer to r16508 (407ch) ldo7 sleep control 15:13 ldo7_slp_sl ot [2:0] 000 ldo7 sleep slot select 000 = sleep voltage / operating mode transition in timeslot 5 001 = disable in timeslot 5 010 = disable in timeslot 4 011 = disable in timeslot 3 100 = disable in timeslot 2 101 = disable in timeslot 1
WM8310 pre-production w pp, may 2012, rev 3.1 246 register address bit label default description refer to 110 = sleep voltage / operating mode transition in timeslot 3 111 = sleep voltage / operating mode transition in timeslot 1 if ldo7 is assigned to a hardware enable input, then codes 001-101 select in which timeslot the regulator enters its sleep condition. 8 ldo7_slp_m ode 1 ldo7 sleep operating mode 0 = normal mode 1 = low power mode 4:0 ldo7_slp_vs el [4:0] 0_0000 ldo7 sleep voltage select 1.0v to 1.6v in 50mv steps 1.7v to 3.5v in 100mv steps 00h = 1.00v 01h = 1.05v 02h = 1.10v ? 0ch = 1.60v 0dh = 1.70v ? 1eh = 3.40v 1fh = 3.50v register 407ch ldo7 sleep control register address bit label default description refer to r16509 (407dh) ldo8 control 15:14 ldo8_err_a ct [1:0] 00 ldo8 error action (undervoltage) 00 = ignore 01 = shut down regulator 10 = shut down system (device reset) 11 = reserved note that an interrupt is always raised. 12:11 ldo8_hwc_s rc [1:0] 00 ldo8 hardware control source 00 = disabled 01 = hardware control 1 10 = hardware control 2 11 = hardware control 1 or 2 10 ldo8_hwc_v sel 0 ldo8 hardware control voltage select 0 = set by ldo8_on_vsel 1 = set by ldo8_slp_vsel 9:8 ldo8_hwc_m ode [1:0] 10 ldo8 hardware control operating mode 00 = low power mode 01 = turn converter off 10 = low power mode 11 = set by ldo8_on_mode 7 ldo8_flt 0 ldo8 output float 0 = ldo8 output discharged when disabled 1 = ldo8 output floating when disabled 6 ldo8_swi 0 ldo8 switch mode 0 = ldo mode 1 = switch mode register 407dh ldo8 control
pre-production WM8310 w pp, may 2012, rev 3.1 247 register address bit label default description refer to r16510 (407eh) ldo8 on control 15:13 ldo8_on_sl ot [2:0] 000 ldo8 on slot select 000 = do not enable 001 = enable in timeslot 1 010 = enable in timeslot 2 011 = enable in timeslot 3 100 = enable in timeslot 4 101 = enable in timeslot 5 110 = controlled by hardware enable 1 111 = controlled by hardware enable 2 8 ldo8_on_mo de 0 ldo8 on operating mode 0 = normal mode 1 = low power mode 4:0 ldo8_on_vs el [4:0] 0_0000 ldo8 on voltage select 1.0v to 1.6v in 50mv steps 1.7v to 3.5v in 100mv steps 00h = 1.00v 01h = 1.05v 02h = 1.10v ? 0ch = 1.60v 0dh = 1.70v ? 1eh = 3.40v 1fh = 3.50v register 407eh ldo8 on control register address bit label default description refer to r16511 (407fh) ldo8 sleep control 15:13 ldo8_slp_sl ot [2:0] 000 ldo8 sleep slot select 000 = sleep voltage / operating mode transition in timeslot 5 001 = disable in timeslot 5 010 = disable in timeslot 4 011 = disable in timeslot 3 100 = disable in timeslot 2 101 = disable in timeslot 1 110 = sleep voltage / operating mode transition in timeslot 3 111 = sleep voltage / operating mode transition in timeslot 1 if ldo8 is assigned to a hardware enable input, then codes 001-101 select in which timeslot the regulator enters its sleep condition. 8 ldo8_slp_m ode 1 ldo8 sleep operating mode 0 = normal mode 1 = low power mode 4:0 ldo8_slp_vs el [4:0] 0_0000 ldo8 sleep voltage select 1.0v to 1.6v in 50mv steps 1.7v to 3.5v in 100mv steps 00h = 1.00v 01h = 1.05v 02h = 1.10v
WM8310 pre-production w pp, may 2012, rev 3.1 248 register address bit label default description refer to ? 0ch = 1.60v 0dh = 1.70v ? 1eh = 3.40v 1fh = 3.50v register 407fh ldo8 sleep control register address bit label default description refer to r16512 (4080h) ldo9 control 15:14 ldo9_err_a ct [1:0] 00 ldo9 error action (undervoltage) 00 = ignore 01 = shut down regulator 10 = shut down system (device reset) 11 = reserved note that an interrupt is always raised. 12:11 ldo9_hwc_s rc [1:0] 00 ldo9 hardware control source 00 = disabled 01 = hardware control 1 10 = hardware control 2 11 = hardware control 1 or 2 10 ldo9_hwc_v sel 0 ldo9 hardware control voltage select 0 = set by ldo9_on_vsel 1 = set by ldo9_slp_vsel 9:8 ldo9_hwc_m ode [1:0] 10 ldo9 hardware control operating mode 00 = low power mode 01 = turn converter off 10 = low power mode 11 = set by ldo9_on_mode 7 ldo9_flt 0 ldo9 output float 0 = ldo9 output discharged when disabled 1 = ldo9 output floating when disabled 6 ldo9_swi 0 ldo9 switch mode 0 = ldo mode 1 = switch mode register 4080h ldo9 control register address bit label default description refer to r16513 (4081h) ldo9 on control 15:13 ldo9_on_sl ot [2:0] 000 ldo9 on slot select 000 = do not enable 001 = enable in timeslot 1 010 = enable in timeslot 2 011 = enable in timeslot 3 100 = enable in timeslot 4 101 = enable in timeslot 5 110 = controlled by hardware enable 1 111 = controlled by hardware enable 2 8 ldo9_on_mo de 0 ldo9 on operating mode 0 = normal mode 1 = low power mode
pre-production WM8310 w pp, may 2012, rev 3.1 249 register address bit label default description refer to 4:0 ldo9_on_vs el [4:0] 0_0000 ldo9 on voltage select 1.0v to 1.6v in 50mv steps 1.7v to 3.5v in 100mv steps 00h = 1.00v 01h = 1.05v 02h = 1.10v ? 0ch = 1.60v 0dh = 1.70v ? 1eh = 3.40v 1fh = 3.50v register 4081h ldo9 on control register address bit label default description refer to r16514 (4082h) ldo9 sleep control 15:13 ldo9_slp_sl ot [2:0] 000 ldo9 sleep slot select 000 = sleep voltage / operating mode transition in timeslot 5 001 = disable in timeslot 5 010 = disable in timeslot 4 011 = disable in timeslot 3 100 = disable in timeslot 2 101 = disable in timeslot 1 110 = sleep voltage / operating mode transition in timeslot 3 111 = sleep voltage / operating mode transition in timeslot 1 if ldo9 is assigned to a hardware enable input, then codes 001-101 select in which timeslot the regulator enters its sleep condition. 8 ldo9_slp_m ode 1 ldo9 sleep operating mode 0 = normal mode 1 = low power mode 4:0 ldo9_slp_vs el [4:0] 0_0000 ldo9 sleep voltage select 1.0v to 1.6v in 50mv steps 1.7v to 3.5v in 100mv steps 00h = 1.00v 01h = 1.05v 02h = 1.10v ? 0ch = 1.60v 0dh = 1.70v ? 1eh = 3.40v 1fh = 3.50v register 4082h ldo9 sleep control
WM8310 pre-production w pp, may 2012, rev 3.1 250 register address bit label default description refer to r16515 (4083h) ldo10 control 15:14 ldo10_err_ act [1:0] 00 ldo10 error action (undervoltage) 00 = ignore 01 = shut down regulator 10 = shut down system (device reset) 11 = reserved note that an interrupt is always raised. 12:11 ldo10_hwc_ src [1:0] 00 ldo10 hardware control source 00 = disabled 01 = hardware control 1 10 = hardware control 2 11 = hardware control 1 or 2 10 ldo10_hwc_ vsel 0 ldo10 hardware control voltage select 0 = set by ldo10_on_vsel 1 = set by ldo10_slp_vsel 9:8 ldo10_hwc_ mode [1:0] 10 ldo10 hardware control operating mode 00 = low power mode 01 = turn converter off 10 = low power mode 11 = set by ldo10_on_mode 7 ldo10_flt 0 ldo10 output float 0 = ldo10 output discharged when disabled 1 = ldo10 output floating when disabled 6 ldo10_swi 0 ldo10 switch mode 0 = ldo mode 1 = switch mode register 4083h ldo10 control register address bit label default description refer to r16516 (4084h) ldo10 on control 15:13 ldo10_on_sl ot [2:0] 000 ldo10 on slot select 000 = do not enable 001 = enable in timeslot 1 010 = enable in timeslot 2 011 = enable in timeslot 3 100 = enable in timeslot 4 101 = enable in timeslot 5 110 = controlled by hardware enable 1 111 = controlled by hardware enable 2 8 ldo10_on_m ode 0 ldo10 on operating mode 0 = normal mode 1 = low power mode 4:0 ldo10_on_v sel [4:0] 0_0000 ldo10 on voltage select 1.0v to 1.6v in 50mv steps 1.7v to 3.5v in 100mv steps 00h = 1.00v 01h = 1.05v 02h = 1.10v ? 0ch = 1.60v 0dh = 1.70v ?
pre-production WM8310 w pp, may 2012, rev 3.1 251 register address bit label default description refer to 1eh = 3.40v 1fh = 3.50v register 4084h ldo10 on control register address bit label default description refer to r16517 (4085h) ldo10 sleep control 15:13 ldo10_slp_s lot [2:0] 000 ldo10 sleep slot select 000 = sleep voltage / operating mode transition in timeslot 5 001 = disable in timeslot 5 010 = disable in timeslot 4 011 = disable in timeslot 3 100 = disable in timeslot 2 101 = disable in timeslot 1 110 = sleep voltage / operating mode transition in timeslot 3 111 = sleep voltage / operating mode transition in timeslot 1 if ldo10 is assigned to a hardware enable input, then codes 001-101 select in which timeslot the regulator enters its sleep condition. 8 ldo10_slp_m ode 1 ldo10 sleep operating mode 0 = normal mode 1 = low power mode 4:0 ldo10_slp_v sel [4:0] 0_0000 ldo10 sleep voltage select 1.0v to 1.6v in 50mv steps 1.7v to 3.5v in 100mv steps 00h = 1.00v 01h = 1.05v 02h = 1.10v ? 0ch = 1.60v 0dh = 1.70v ? 1eh = 3.40v 1fh = 3.50v register 4085h ldo10 sleep control register address bit label default description refer to r16519 (4087h) ldo11 on control 15:13 ldo11_on_sl ot [2:0] 000 ldo11 on slot select 000 = do not enable 001 = enable in timeslot 1 010 = enable in timeslot 2 011 = enable in timeslot 3 100 = enable in timeslot 4 101 = enable in timeslot 5 110 = controlled by hardware enable 1 111 = controlled by hardware enable 2
WM8310 pre-production w pp, may 2012, rev 3.1 252 register address bit label default description refer to 12 ldo11_frce na 0 ldo11 force enable (forces ldo11 to be enabled at all times in the off, on and sleep states) 0 = disabled 1 = enabled 7 ldo11_vsel_ src 0 ldo11 voltage select source 0 = normal (ldo11 settings) 1 = same as dc-dc converter 1 3:0 ldo11_on_v sel [3:0] 0000 ldo11 on voltage select 0.80v to 1.55v in 50mv steps 0h = 0.80v 1h = 0.85v 2h = 0.90v ? eh = 1.50v fh = 1.55v register 4087h ldo11 on control register address bit label default description refer to r16520 (4088h) ldo11 sleep control 15:13 ldo11_slp_s lot [2:0] 000 ldo11 sleep slot select 000 = sleep voltage / operating mode transition in timeslot 5 001 = disable in timeslot 5 010 = disable in timeslot 4 011 = disable in timeslot 3 100 = disable in timeslot 2 101 = disable in timeslot 1 110 = sleep voltage / operating mode transition in timeslot 3 111 = sleep voltage / operating mode transition in timeslot 1 if ldo11 is assigned to a hardware enable input, then codes 001-101 select in which timeslot the regulator enters its sleep condition. 3:0 ldo11_slp_v sel [3:0] 0000 ldo11 sleep voltage select 0.80v to 1.55v in 50mv steps 0h = 0.80v 1h = 0.85v 2h = 0.90v ? eh = 1.50v fh = 1.55v register 4088h ldo11 sleep control
pre-production WM8310 w pp, may 2012, rev 3.1 253 register address bit label default description refer to r16526 (408eh) power good source 1 3 dc4_ok 0 dc-dc4 status selected as an input to pwr_good 0 = disabled 1 = enabled 2 dc3_ok 1 dc-dc3 status selected as an input to pwr_good 0 = disabled 1 = enabled 1 dc2_ok 1 dc-dc2 status selected as an input to pwr_good 0 = disabled 1 = enabled 0 dc1_ok 1 dc-dc1 status selected as an input to pwr_good 0 = disabled 1 = enabled register 408eh power good source 1 register address bit label default description refer to r16527 (408fh) power good source 2 9 ldo10_ok 1 ldo10 status selected as an input to pwr_good 0 = disabled 1 = enabled 8 ldo9_ok 1 ldo9 status selected as an input to pwr_good 0 = disabled 1 = enabled 7 ldo8_ok 1 ldo8 status selected as an input to pwr_good 0 = disabled 1 = enabled 6 ldo7_ok 1 ldo7 status selected as an input to pwr_good 0 = disabled 1 = enabled 5 ldo6_ok 1 ldo6 status selected as an input to pwr_good 0 = disabled 1 = enabled 4 ldo5_ok 1 ldo5 status selected as an input to pwr_good 0 = disabled 1 = enabled 3 ldo4_ok 1 ldo4 status selected as an input to pwr_good 0 = disabled 1 = enabled 2 ldo3_ok 1 ldo3 status selected as an input to pwr_good 0 = disabled 1 = enabled 1 ldo2_ok 1 ldo2 status selected as an input to pwr_good 0 = disabled 1 = enabled 0 ldo1_ok 1 ldo1 status selected as an input to pwr_good 0 = disabled 1 = enabled register 408fh power good source 2
WM8310 pre-production w pp, may 2012, rev 3.1 254 register address bit label default description refer to r16528 (4090h) clock control 1 15 clkout_ena 0 clkout output enable 0 = disabled 1 = enabled protected by security key 13 clkout_od 0 clkout pin configuration 0 = cmos 1 = open drain 10:8 clkout_slo t [2:0] 000 clkout output enable on slot select 000 = do not enable 001 = enable in timeslot 1 010 = enable in timeslot 2 011 = enable in timeslot 3 100 = enable in timeslot 4 101 = enable in timeslot 5 110 = do not enable 111 = do not enable 6:4 clkout_slp slot [2:0] 000 clkout output sleep slot select 000 = controlled by clkout_ena 001 = disable in timeslot 5 010 = disable in timeslot 4 011 = disable in timeslot 3 100 = disable in timeslot 2 101 = disable in timeslot 1 110 = controlled by clkout_ena 111 = controlled by clkout_ena 0 clkout_src 0 clkout output source select 0 = fll output 1 = 32.768khz oscillator register 4090h clock control 1 register address bit label default description refer to r16529 (4091h) clock control 2 15 xtal_inh 0 crystal start-up inhibit 0 = disabled 1 = enabled when xtal_inh=1, the ?on? tr ansition is inhibited until the crystal oscillator is valid 13 xtal_ena 0 crystal oscillator enable 0 = disabled at all times 1 = enabled in off, on and sleep states (note that the backup behaviour is determined by xtal_bkupena.) 12 xtal_bkupe na 1 selects the rtc and 32.768khz oscillator in backup state 0 = rtc unclocked in backup 1 = rtc maintained in backup (note that xtal_ena must also be set if the rtc is to be maintained in backup.)
pre-production WM8310 w pp, may 2012, rev 3.1 255 register address bit label default description refer to 7 fll_auto 1 fll automatic mode enable 0 = manual configuration mode 1 = automatic configuration mode (to enable the fll output, fll_ena must also be set in automatic mode) 2:0 fll_auto_fr eq [2:0] 000 fll automatic mode frequency select 000 = 2.048mhz 001 = 11.2896mhz 010 = 12mhz 011 = 12.288mhz 100 = 19.2mhz 101 = 22.5792mhz 110 = 24mhz 111 = 24.576mhz register 4091h clock control 2 register address bit label default description refer to r16530 (4092h) fll control 1 2 fll_frac 0 fractional enable 0 = integer mode 1 = fractional mode integer mode offers reduced power consumption. fractional mode offers best fll performance, provided also that n.k is a non-integer value. 0 fll_ena 0 fll enable 0 = disabled 1 = enabled note - this bit is reset to 0 when the off power state is entered. register 4092h fll control 1 register address bit label default description refer to r16531 (4093h) fll control 2 13:8 fll_outdiv [5:0] 00_0000 fout clock divider 000000 = reserved 000001 = reserved 000010 = reserved 000011 = 4 000100 = 5 000101 = 6 ? 111110 = 63 111111 = 64 (fout = fvco / fll_outdiv) 6:4 fll_ctrl_ra te [2:0] 000 frequency of the fll control block 000 = fvco / 1 (recommended value) 001 = fvco / 2 010 = fvco / 3 011 = fvco / 4 100 = fvco / 5 101 = fvco / 6
WM8310 pre-production w pp, may 2012, rev 3.1 256 register address bit label default description refer to 110 = fvco / 7 111 = fvco / 8 recommended that this register is not changed from default. 2:0 fll_fratio [2:0] 000 fvco clock divider 000 = 1 001 = 2 010 = 4 011 = 8 1xx = 16 000 recommended for high fref 011 recommended for low fref register 4093h fll control 2 register address bit label default description refer to r16532 (4094h) fll control 3 15:0 fll_k [15:0] 0000_0000 _0000_000 0 fractional multiply for fref (msb = 0.5) register 4094h fll control 3 register address bit label default description refer to r16533 (4095h) fll control 4 14:5 fll_n [9:0] 01_0111_0 111 integer multiply for fref (lsb = 1) 3:0 fll_gain [3:0] 0000 gain applied to error 0000 = x 1 (recommended value) 0001 = x 2 0010 = x 4 0011 = x 8 0100 = x 16 0101 = x 32 0110 = x 64 0111 = x 128 1xxx = x 256 recommended that this register is not changed from default. register 4095h fll control 4
pre-production WM8310 w pp, may 2012, rev 3.1 257 register address bit label default description refer to r16534 (4096h) fll control 5 4:3 fll_clk_ref _div [1:0] 00 fll clock reference divider 00 = 1 01 = 2 10 = 4 11 = 8 clkin must be divided down to <=13.5mhz. for lower power operation, the reference clock can be divided down further if desired. 1:0 fll_clk_src [1:0] 00 fll clock source 00 = 32.768khz xtal oscillator 01 = clkin 10 = reserved 11 = reserved register 4096h fll control 5 register address bit label default description refer to r30720 (7800h) unique id 1 15:0 unique_id [15:0] 0000_0000 _0000_000 0 unique id, word 7 register 7800h unique id 1 register address bit label default description refer to r30721 (7801h) unique id 2 15:0 unique_id [15:0] 0000_0000 _0000_000 0 unique id, word 6 register 7801h unique id 2 register address bit label default description refer to r30722 (7802h) unique id 3 15:0 unique_id [15:0] 0000_0000 _0000_000 0 unique id, word 5 register 7802h unique id 3 register address bit label default description refer to r30723 (7803h) unique id 4 15:0 unique_id [15:0] 0000_0000 _0000_000 0 unique id, word 4 register 7803h unique id 4 register address bit label default description refer to r30724 (7804h) unique id 5 15:0 unique_id [15:0] 0000_0000 _0000_000 0 unique id, word 3 register 7804h unique id 5
WM8310 pre-production w pp, may 2012, rev 3.1 258 register address bit label default description refer to r30725 (7805h) unique id 6 15:0 unique_id [15:0] 0000_0000 _0000_000 0 unique id, word 2 register 7805h unique id 6 register address bit label default description refer to r30726 (7806h) unique id 7 15:0 unique_id [15:0] 0000_0000 _0000_000 0 unique id, word 1 register 7806h unique id 7 register address bit label default description refer to r30727 (7807h) unique id 8 15:0 unique_id [15:0] 0000_0000 _0000_000 0 unique id, word 0 register 7807h unique id 8 register address bit label default description refer to r30728 (7808h) factory otp id 15:1 otp_fact_id [14:0] 000_0000_ 0000_0000 [no description available] 0 otp_fact_fi nal 0 [no description available] register 7808h factory otp id register address bit label default description refer to r30729 (7809h) factory otp 1 15:12 dc3_trim [3:0] 0000 [no description available] 11:6 dc2_trim [5:0] 00_0000 [no description available] 5:0 dc1_trim [5:0] 00_0000 [no description available] register 7809h factory otp 1 register address bit label default description refer to r30730 (780ah) factory otp 2 15:0 chip_id [15:0] 0000_0000 _0000_000 0 [no description available] register 780ah factory otp 2
pre-production WM8310 w pp, may 2012, rev 3.1 259 register address bit label default description refer to r30731 (780bh) factory otp 3 10:7 osc_trim [3:0] 0000 [no description available] 6:3 bg_trim [3:0] 0000 [no description available] 2:0 lpbg_trim [2:0] 000 [no description available] register 780bh factory otp 3 register address bit label default description refer to r30732 (780ch) factory otp 4 7:1 child_i2c_a ddr [6:0] 000_0000 [no description available] 0 ch_aw 0 [no description available] register 780ch factory otp 4 register address bit label default description refer to r30733 (780dh) factory otp 5 5:0 charge_tri m [5:0] 00_0000 [no description available] register 780dh factory otp 5 register address bit label default description refer to r30736 (7810h) customer otp id 15 otp_auto_p rog 0 if this bit is set when bootstrap data is loaded from ice (in development mode), then the ice contents will be programmed in the otp. 14:1 otp_cust_id [13:0] 00_0000_0 000_0000 this field is checked w hen an ?on? transition is requested. a non-zero value is used to confirm valid data. 0 otp_cust_fi nal 0 if otp_cust_final is set in the otp and also set in the dcrw, then no further writes are possible to the otp. register 7810h customer otp id register address bit label default description refer to r30737 (7811h) dc1 otp control 15:13 dc1_on_slo t [2:0] 000 dc-dc1 on slot select 000 = do not enable 001 = enable in timeslot 1 010 = enable in timeslot 2 011 = enable in timeslot 3 100 = enable in timeslot 4 101 = enable in timeslot 5 110 = controlled by hardware enable 1 111 = controlled by hardware enable 2
WM8310 pre-production w pp, may 2012, rev 3.1 260 register address bit label default description refer to 9:8 dc1_freq [1:0] 00 dc-dc1 switching frequency 00 = reserved 01 = 2.0mhz 10 = reserved 11 = 4.0mhz 7 dc1_phase 0 dc-dc1 clock phase control 0 = normal 1 = inverted 6:2 dc1_on_vse l [6:2] 0_0000 dc-dc1 on voltage select dc1_on_vsel [6:0] selects the dc-dc1 output voltage from 0.6v to 1.8v in 12.5mv steps. dc1_on_vsel [6:2] controls the voltage in 50mv steps. dc1_on_vsel [6:0] is coded as follows: 00h to 08h = 0.6v 09h = 0.6125v ? 48h = 1.4v (see note) ? 67h = 1.7875v 68h to 7fh = 1.8v note - maximum output voltage selection in 4mhz switching mode is 48h (1.4v). 1:0 dc1_cap [1:0] 00 dc-dc1 output capacitor 00 = 4.7uf to 20uf 01 = reserved 10 = 22uf to 47uf 11 = reserved register 7811h dc1 otp control register address bit label default description refer to r30738 (7812h) dc2 otp control 15:13 dc2_on_slo t [2:0] 000 dc-dc2 on slot select 000 = do not enable 001 = enable in timeslot 1 010 = enable in timeslot 2 011 = enable in timeslot 3 100 = enable in timeslot 4 101 = enable in timeslot 5 110 = controlled by hardware enable 1 111 = controlled by hardware enable 2 9:8 dc2_freq [1:0] 00 dc-dc2 switching frequency 00 = reserved 01 = 2.0mhz 10 = reserved 11 = 4.0mhz 7 dc2_phase 1 dc-dc2 clock phase control 0 = normal 1 = inverted
pre-production WM8310 w pp, may 2012, rev 3.1 261 register address bit label default description refer to 6:2 dc2_on_vse l [6:2] 0_0000 dc-dc2 on voltage select dc2_on_vsel [6:0] selects the dc-dc2 output voltage from 0.6v to 1.8v in 12.5mv steps. dc2_on_vsel [6:2] controls the voltage in 50mv steps. dc2_on_vsel [6:0] is coded as follows: 00h to 08h = 0.6v 09h = 0.6125v ? 48h = 1.4v (see note) ? 67h = 1.7875v 68h to 7fh = 1.8v note - maximum output voltage selection in 4mhz switching mode is 48h (1.4v). 1:0 dc2_cap [1:0] 00 dc-dc2 output capacitor 00 = 4.7uf to 20uf 01 = reserved 10 = 22uf to 47uf 11 = reserved register 7812h dc2 otp control register address bit label default description refer to r30739 (7813h) dc3 otp control 15:13 dc3_on_slo t [2:0] 000 dc-dc3 on slot select 000 = do not enable 001 = enable in timeslot 1 010 = enable in timeslot 2 011 = enable in timeslot 3 100 = enable in timeslot 4 101 = enable in timeslot 5 110 = controlled by hardware enable 1 111 = controlled by hardware enable 2 7 dc3_phase 0 dc-dc3 clock phase control 0 = normal 1 = inverted 6:2 dc3_on_vse l [6:2] 0_0000 dc-dc3 on voltage select dc3_on_vsel [6:0] selects the dc-dc3 output voltage from 0.85v to 3.4v in 25mv steps. dc3_on_vsel [6:2] controls the voltage in 100mv steps. dc3_on_vsel [6:0] is coded as follows: 00h = 0.85v 01h = 0.875v ? 65h = 3.375v 66h to 7fh = 3.4v
WM8310 pre-production w pp, may 2012, rev 3.1 262 register address bit label default description refer to 1:0 dc3_cap [1:0] 00 dc-dc3 output capacitor 00 = 10uf to 20uf 01 = 10uf to 20uf 10 = 22uf to 45uf 11 = 47uf to 100uf register 7813h dc3 otp control register address bit label default description refer to r30740 (7814h) ldo1/2 otp control 15:13 ldo2_on_sl ot [2:0] 000 ldo2 on slot select 000 = do not enable 001 = enable in timeslot 1 010 = enable in timeslot 2 011 = enable in timeslot 3 100 = enable in timeslot 4 101 = enable in timeslot 5 110 = controlled by hardware enable 1 111 = controlled by hardware enable 2 12:8 ldo2_on_vs el [4:0] 0_0000 ldo2 on voltage select 0.9v to 1.6v in 50mv steps 1.7v to 3.3v in 100mv steps 00h = 0.90v 01h = 0.95v ? 0eh = 1.60v 0fh = 1.70v ? 1eh = 3.20v 1fh = 3.30v 7:5 ldo1_on_sl ot [2:0] 000 ldo1 on slot select 000 = do not enable 001 = enable in timeslot 1 010 = enable in timeslot 2 011 = enable in timeslot 3 100 = enable in timeslot 4 101 = enable in timeslot 5 110 = controlled by hardware enable 1 111 = controlled by hardware enable 2 4:0 ldo1_on_vs el [4:0] 0_0000 ldo1 on voltage select 0.9v to 1.6v in 50mv steps 1.7v to 3.3v in 100mv steps 00h = 0.90v 01h = 0.95v ? 0eh = 1.60v 0fh = 1.70v ? 1eh = 3.20v 1fh = 3.30v register 7814h ldo1/2 otp control
pre-production WM8310 w pp, may 2012, rev 3.1 263 register address bit label default description refer to r30741 (7815h) ldo3/4 otp control 15:13 ldo4_on_sl ot [2:0] 000 ldo4 on slot select 000 = do not enable 001 = enable in timeslot 1 010 = enable in timeslot 2 011 = enable in timeslot 3 100 = enable in timeslot 4 101 = enable in timeslot 5 110 = controlled by hardware enable 1 111 = controlled by hardware enable 2 12:8 ldo4_on_vs el [4:0] 0_0000 ldo4 on voltage select 0.9v to 1.6v in 50mv steps 1.7v to 3.3v in 100mv steps 00h = 0.90v 01h = 0.95v ? 0eh = 1.60v 0fh = 1.70v ? 1eh = 3.20v 1fh = 3.30v 7:5 ldo3_on_sl ot [2:0] 000 ldo3 on slot select 000 = do not enable 001 = enable in timeslot 1 010 = enable in timeslot 2 011 = enable in timeslot 3 100 = enable in timeslot 4 101 = enable in timeslot 5 110 = controlled by hardware enable 1 111 = controlled by hardware enable 2 4:0 ldo3_on_vs el [4:0] 0_0000 ldo3 on voltage select 0.9v to 1.6v in 50mv steps 1.7v to 3.3v in 100mv steps 00h = 0.90v 01h = 0.95v ? 0eh = 1.60v 0fh = 1.70v ? 1eh = 3.20v 1fh = 3.30v register 7815h ldo3/4 otp control
WM8310 pre-production w pp, may 2012, rev 3.1 264 register address bit label default description refer to r30742 (7816h) ldo5/6 otp control 15:13 ldo6_on_sl ot [2:0] 000 ldo6 on slot select 000 = do not enable 001 = enable in timeslot 1 010 = enable in timeslot 2 011 = enable in timeslot 3 100 = enable in timeslot 4 101 = enable in timeslot 5 110 = controlled by hardware enable 1 111 = controlled by hardware enable 2 12:8 ldo6_on_vs el [4:0] 0_0000 ldo6 on voltage select 0.9v to 1.6v in 50mv steps 1.7v to 3.3v in 100mv steps 00h = 0.90v 01h = 0.95v ? 0eh = 1.60v 0fh = 1.70v ? 1eh = 3.20v 1fh = 3.30v 7:5 ldo5_on_sl ot [2:0] 000 ldo5 on slot select 000 = do not enable 001 = enable in timeslot 1 010 = enable in timeslot 2 011 = enable in timeslot 3 100 = enable in timeslot 4 101 = enable in timeslot 5 110 = controlled by hardware enable 1 111 = controlled by hardware enable 2 4:0 ldo5_on_vs el [4:0] 0_0000 ldo5 on voltage select 0.9v to 1.6v in 50mv steps 1.7v to 3.3v in 100mv steps 00h = 0.90v 01h = 0.95v ? 0eh = 1.60v 0fh = 1.70v ? 1eh = 3.20v 1fh = 3.30v register 7816h ldo5/6 otp control
pre-production WM8310 w pp, may 2012, rev 3.1 265 register address bit label default description refer to r30743 (7817h) ldo7/8 otp control 15:13 ldo8_on_sl ot [2:0] 000 ldo8 on slot select 000 = do not enable 001 = enable in timeslot 1 010 = enable in timeslot 2 011 = enable in timeslot 3 100 = enable in timeslot 4 101 = enable in timeslot 5 110 = controlled by hardware enable 1 111 = controlled by hardware enable 2 12:8 ldo8_on_vs el [4:0] 0_0000 ldo8 on voltage select 1.0v to 1.6v in 50mv steps 1.7v to 3.5v in 100mv steps 00h = 1.00v 01h = 1.05v 02h = 1.10v ? 0ch = 1.60v 0dh = 1.70v ? 1eh = 3.40v 1fh = 3.50v 7:5 ldo7_on_sl ot [2:0] 000 ldo7 on slot select 000 = do not enable 001 = enable in timeslot 1 010 = enable in timeslot 2 011 = enable in timeslot 3 100 = enable in timeslot 4 101 = enable in timeslot 5 110 = controlled by hardware enable 1 111 = controlled by hardware enable 2 4:0 ldo7_on_vs el [4:0] 0_0000 ldo7 on voltage select 1.0v to 1.6v in 50mv steps 1.7v to 3.5v in 100mv steps 00h = 1.00v 01h = 1.05v 02h = 1.10v ? 0ch = 1.60v 0dh = 1.70v ? 1eh = 3.40v 1fh = 3.50v register 7817h ldo7/8 otp control
WM8310 pre-production w pp, may 2012, rev 3.1 266 register address bit label default description refer to r30744 (7818h) ldo9/10 otp control 15:13 ldo10_on_sl ot [2:0] 000 ldo10 on slot select 000 = do not enable 001 = enable in timeslot 1 010 = enable in timeslot 2 011 = enable in timeslot 3 100 = enable in timeslot 4 101 = enable in timeslot 5 110 = controlled by hardware enable 1 111 = controlled by hardware enable 2 12:8 ldo10_on_v sel [4:0] 0_0000 ldo10 on voltage select 1.0v to 1.6v in 50mv steps 1.7v to 3.5v in 100mv steps 00h = 1.00v 01h = 1.05v 02h = 1.10v ? 0ch = 1.60v 0dh = 1.70v ? 1eh = 3.40v 1fh = 3.50v 7:5 ldo9_on_sl ot [2:0] 000 ldo9 on slot select 000 = do not enable 001 = enable in timeslot 1 010 = enable in timeslot 2 011 = enable in timeslot 3 100 = enable in timeslot 4 101 = enable in timeslot 5 110 = controlled by hardware enable 1 111 = controlled by hardware enable 2 4:0 ldo9_on_vs el [4:0] 0_0000 ldo9 on voltage select 1.0v to 1.6v in 50mv steps 1.7v to 3.5v in 100mv steps 00h = 1.00v 01h = 1.05v 02h = 1.10v ? 0ch = 1.60v 0dh = 1.70v ? 1eh = 3.40v 1fh = 3.50v register 7818h ldo9/10 otp control
pre-production WM8310 w pp, may 2012, rev 3.1 267 register address bit label default description refer to r30745 (7819h) ldo11/epe control 15:13 ldo11_on_sl ot [2:0] 000 ldo11 on slot select 000 = do not enable 001 = enable in timeslot 1 010 = enable in timeslot 2 011 = enable in timeslot 3 100 = enable in timeslot 4 101 = enable in timeslot 5 110 = controlled by hardware enable 1 111 = controlled by hardware enable 2 11:8 ldo11_on_v sel [3:0] 0000 ldo11 on voltage select 0.80v to 1.55v in 50mv steps 0h = 0.80v 1h = 0.85v 2h = 0.90v ? eh = 1.50v fh = 1.55v 7:5 epe2_on_sl ot [2:0] 000 epe2 on slot select 000 = do not enable 001 = enable in timeslot 1 010 = enable in timeslot 2 011 = enable in timeslot 3 100 = enable in timeslot 4 101 = enable in timeslot 5 110 = controlled by hardware enable 1 111 = controlled by hardware enable 2 4:2 epe1_on_sl ot [2:0] 000 epe1 on slot select 000 = do not enable 001 = enable in timeslot 1 010 = enable in timeslot 2 011 = enable in timeslot 3 100 = enable in timeslot 4 101 = enable in timeslot 5 110 = controlled by hardware enable 1 111 = controlled by hardware enable 2 1:0 usb100ma_s tartup [1:0] 00 sets the device behaviour when starting up under usb power, when usb_ilim = 010b (100ma) 00 = normal 01 = soft-start 10 = only start if battvdd > 3.1v 11 = only start if battvdd > 3.4v in the 1x modes, if the battery voltage is less than the selected threshold, then the device will enable trickle charge mode instead of executing the start-up request. the start-up request is delayed until the battery voltage threshold has been met. register 7819h ldo11/epe control
WM8310 pre-production w pp, may 2012, rev 3.1 268 register address bit label default description refer to r30746 (781ah) gpio1 otp control 15 gp1_dir 1 gpio1 pin direction 0 = output 1 = input 14:13 gp1_pull [1:0] 01 gpio1 pull-up / pull-down configuration 00 = no pull resistor 01 = pull-down enabled 10 = pull-up enabled 11 = reserved 12 gp1_int_mod e 0 gpio1 interrupt mode 0 = gpio interrupt is rising edge triggered (if gp1_pol=1) or falling edge triggered (if gp1_pol=0) 1 = gpio interrupt is triggered on rising and falling edges 11 gp1_pwr_do m 0 gpio1 power domain select 0 = dbvdd 1 = pmicvdd (ldo12) 10 gp1_pol 1 gpio1 polarity select 0 = inverted (active low) 1 = non-inverted (active high) 9 gp1_od 0 gpio1 output pin configuration 0 = cmos 1 = open drain 8 gp1_ena 0 gpio1 enable control 0 = gpio pin is tri-stated 1 = normal operation 7:4 gp1_fn [3:0] 0000 gpio1 pin function input functions: 0 = gpio input (long de-bounce) 1 = gpio input 2 = power on/off request 3 = sleep/wake request 4 = sleep/wake request (long de-bounce) 5 = sleep request 6 = power on request 7 = watchdog reset input 8 = dvs1 input 9 = dvs2 input 10 = hw enable1 input 11 = hw enable2 input 12 = hw control1 input 13 = hw control2 input 14 = hw control1 input (long de-bounce) 15 = hw control2 input (long de-bounce) output functions: 0 = gpio output 1 = 32.768khz oscillator output 2 = on state 3 = sleep state 4 = power state change 5 = reserved 6 = reserved 7 = reserved
pre-production WM8310 w pp, may 2012, rev 3.1 269 register address bit label default description refer to 8 = dc-dc1 dvs done 9 = dc-dc2 dvs done 10 = external power enable1 11 = external power enable2 12 = system supply good (sysok) 13 = converter power good (pwr_good) 14 = external power clock (2mhz) 15 = auxiliary reset 3 clkout_src 0 clkout output source select 0 = fll output 1 = 32.768khz oscillator 1 xtal_inh 0 crystal start-up inhibit 0 = disabled 1 = enabled when xtal_inh=1, the ?on? tr ansition is inhibited until the crystal oscillator is valid 0 chg_ena 0 battery charger enable 0 = disable 1 = enable protected by security key. register 781ah gpio1 otp control register address bit label default description refer to r30747 (781bh) gpio2 otp control 15 gp2_dir 1 gpio2 pin direction 0 = output 1 = input 14:13 gp2_pull [1:0] 01 gpio2 pull-up / pull-down configuration 00 = no pull resistor 01 = pull-down enabled 10 = pull-up enabled 11 = reserved 12 gp2_int_mod e 0 gpio2 interrupt mode 0 = gpio interrupt is rising edge triggered (if gp2_pol=1) or falling edge triggered (if gp2_pol=0) 1 = gpio interrupt is triggered on rising and falling edges 11 gp2_pwr_do m 0 gpio2 power domain select 0 = dbvdd 1 = pmicvdd (ldo12) 10 gp2_pol 1 gpio2 polarity select 0 = inverted (active low) 1 = non-inverted (active high) 9 gp2_od 0 gpio2 output pin configuration 0 = cmos 1 = open drain 8 gp2_ena 0 gpio2 enable control 0 = gpio pin is tri-stated 1 = normal operation
WM8310 pre-production w pp, may 2012, rev 3.1 270 register address bit label default description refer to 7:4 gp2_fn [3:0] 0000 gpio2 pin function input functions: 0 = gpio input (long de-bounce) 1 = gpio input 2 = power on/off request 3 = sleep/wake request 4 = sleep/wake request (long de-bounce) 5 = sleep request 6 = power on request 7 = watchdog reset input 8 = dvs1 input 9 = dvs2 input 10 = hw enable1 input 11 = hw enable2 input 12 = hw control1 input 13 = hw control2 input 14 = hw control1 input (long de-bounce) 15 = hw control2 input (long de-bounce) output functions: 0 = gpio output 1 = 32.768khz oscillator output 2 = on state 3 = sleep state 4 = power state change 5 = reserved 6 = reserved 7 = reserved 8 = dc-dc1 dvs done 9 = dc-dc2 dvs done 10 = external power enable1 11 = external power enable2 12 = system supply good (sysok) 13 = converter power good (pwr_good) 14 = external power clock (2mhz) 15 = auxiliary reset 3:1 clkout_slo t [2:0] 000 clkout output enable slot select 000 = do not enable 001 = enable in timeslot 1 010 = enable in timeslot 2 011 = enable in timeslot 3 100 = enable in timeslot 4 101 = enable in timeslot 5 110 = controlled by hardware enable 1 111 = controlled by hardware enable 2 0 wdog_ena 1 watchdog timer enable 0 = disabled 1 = enabled (enables the watchdog; does not reset it) protected by security key. register 781bh gpio2 otp control
pre-production WM8310 w pp, may 2012, rev 3.1 271 register address bit label default description refer to r30748 (781ch) gpio3 otp control 15 gp3_dir 1 gpio3 pin direction 0 = output 1 = input 14:13 gp3_pull [1:0] 01 gpio3 pull-up / pull-down configuration 00 = no pull resistor 01 = pull-down enabled 10 = pull-up enabled 11 = reserved 12 gp3_int_mod e 0 gpio3 interrupt mode 0 = gpio interrupt is rising edge triggered (if gp3_pol=1) or falling edge triggered (if gp3_pol=0) 1 = gpio interrupt is triggered on rising and falling edges 11 gp3_pwr_do m 0 gpio3 power domain select 0 = dbvdd 1 = pmicvdd (ldo12) 10 gp3_pol 1 gpio3 polarity select 0 = inverted (active low) 1 = non-inverted (active high) 9 gp3_od 0 gpio3 output pin configuration 0 = cmos 1 = open drain 8 gp3_ena 0 gpio3 enable control 0 = gpio pin is tri-stated 1 = normal operation 7:4 gp3_fn [3:0] 0000 gpio3 pin function input functions: 0 = gpio input (long de-bounce) 1 = gpio input 2 = power on/off request 3 = sleep/wake request 4 = sleep/wake request (long de-bounce) 5 = sleep request 6 = power on request 7 = watchdog reset input 8 = dvs1 input 9 = dvs2 input 10 = hw enable1 input 11 = hw enable2 input 12 = hw control1 input 13 = hw control2 input 14 = hw control1 input (long de-bounce) 15 = hw control2 input (long de-bounce) output functions: 0 = gpio output 1 = 32.768khz oscillator output 2 = on state 3 = sleep state 4 = power state change 5 = reserved 6 = reserved 7 = reserved
WM8310 pre-production w pp, may 2012, rev 3.1 272 register address bit label default description refer to 8 = dc-dc1 dvs done 9 = dc-dc2 dvs done 10 = external power enable1 11 = external power enable2 12 = system supply good (sysok) 13 = converter power good (pwr_good) 14 = external power clock (2mhz) 15 = auxiliary reset 3:1 fll_auto_fr eq [2:0] 000 fll automatic mode frequency select 000 = 2.048mhz 001 = 11.2896mhz 010 = 12mhz 011 = 12.288mhz 100 = 19.2mhz 101 = 22.5792mhz 110 = 24mhz 111 = 24.576mhz register 781ch gpio3 otp control register address bit label default description refer to r30749 (781dh) gpio4 otp control 15 gp4_dir 1 gpio4 pin direction 0 = output 1 = input 14:13 gp4_pull [1:0] 01 gpio4 pull-up / pull-down configuration 00 = no pull resistor 01 = pull-down enabled 10 = pull-up enabled 11 = reserved 12 gp4_int_mod e 0 gpio4 interrupt mode 0 = gpio interrupt is rising edge triggered (if gp4_pol=1) or falling edge triggered (if gp4_pol=0) 1 = gpio interrupt is triggered on rising and falling edges 11 gp4_pwr_do m 0 gpio4 power domain select 0 = dbvdd 1 = sysvdd 10 gp4_pol 1 gpio4 polarity select 0 = inverted (active low) 1 = non-inverted (active high) 9 gp4_od 0 gpio4 output pin configuration 0 = cmos 1 = open drain 8 gp4_ena 0 gpio4 enable control 0 = gpio pin is tri-stated 1 = normal operation 7:4 gp4_fn [3:0] 0000 gpio4 pin function input functions: 0 = gpio input (long de-bounce) 1 = gpio input 2 = power on/off request 3 = sleep/wake request
pre-production WM8310 w pp, may 2012, rev 3.1 273 register address bit label default description refer to 4 = sleep/wake request (long de-bounce) 5 = sleep request 6 = power on request 7 = watchdog reset input 8 = dvs1 input 9 = dvs2 input 10 = hw enable1 input 11 = hw enable2 input 12 = hw control1 input 13 = hw control2 input 14 = hw control1 input (long de-bounce) 15 = hw control2 input (long de-bounce) output functions: 0 = gpio output 1 = 32.768khz oscillator output 2 = on state 3 = sleep state 4 = power state change 5 = reserved 6 = reserved 7 = reserved 8 = dc-dc1 dvs done 9 = dc-dc2 dvs done 10 = external power enable1 11 = external power enable2 12 = system supply good (sysok) 13 = converter power good (pwr_good) 14 = external power clock (2mhz) 15 = auxiliary reset 3:2 led1_src [1:0] 11 l ed1 source selects the led1 function.) 0 0 = off 0 1 = power state status 1 0 = charger status 1 1 = manual mode note - led1 also indicates completion of otp auto program 1:0 led2_src [1:0] 11 l ed2 source selects the led2 function.) 0 0 = off 0 1 = power state status 1 0 = charger status 1 1 = manual mode note - led2 also indicates an otp auto program error condition register 781dh gpio4 otp control
WM8310 pre-production w pp, may 2012, rev 3.1 274 register address bit label default description refer to r30750 (781eh) gpio5 otp control 15 gp5_dir 1 gpio5 pin direction 0 = output 1 = input 14:13 gp5_pull [1:0] 01 gpio5 pull-up / pull-down configuration 00 = no pull resistor 01 = pull-down enabled 10 = pull-up enabled 11 = reserved 12 gp5_int_mod e 0 gpio5 interrupt mode 0 = gpio interrupt is rising edge triggered (if gp5_pol=1) or falling edge triggered (if gp5_pol=0) 1 = gpio interrupt is triggered on rising and falling edges 11 gp5_pwr_do m 0 gpio5 power domain select 0 = dbvdd 1 = sysvdd 10 gp5_pol 1 gpio5 polarity select 0 = inverted (active low) 1 = non-inverted (active high) 9 gp5_od 0 gpio5 output pin configuration 0 = cmos 1 = open drain 8 gp5_ena 0 gpio5 enable control 0 = gpio pin is tri-stated 1 = normal operation 7:4 gp5_fn [3:0] 0000 gpio5 pin function input functions: 0 = gpio input (long de-bounce) 1 = gpio input 2 = power on/off request 3 = sleep/wake request 4 = sleep/wake request (long de-bounce) 5 = sleep request 6 = power on request 7 = watchdog reset input 8 = dvs1 input 9 = dvs2 input 10 = hw enable1 input 11 = hw enable2 input 12 = hw control1 input 13 = hw control2 input 14 = hw control1 input (long de-bounce) 15 = hw control2 input (long de-bounce) output functions: 0 = gpio output 1 = 32.768khz oscillator output 2 = on state 3 = sleep state 4 = power state change 5 = reserved 6 = reserved 7 = reserved
pre-production WM8310 w pp, may 2012, rev 3.1 275 register address bit label default description refer to 8 = dc-dc1 dvs done 9 = dc-dc2 dvs done 10 = external power enable1 11 = external power enable2 12 = system supply good (sysok) 13 = converter power good (pwr_good) 14 = external power clock (2mhz) 15 = auxiliary reset 3:1 usb_ilim [2:0] 010 sets the usb current limit 000 = 0ma (usb switch is open) 001 = 2.5ma 010 = 100ma 011 = 500ma 100 = 900ma 101 = 1500ma 110 = 1800ma 111 = 550ma register 781eh gpio5 otp control register address bit label default description refer to r30751 (781fh) gpio6 otp control 15 gp6_dir 1 gpio6 pin direction 0 = output 1 = input 14:13 gp6_pull [1:0] 01 gpio6 pull-up / pull-down configuration 00 = no pull resistor 01 = pull-down enabled 10 = pull-up enabled 11 = reserved 12 gp6_int_mod e 0 gpio6 interrupt mode 0 = gpio interrupt is rising edge triggered (if gp6_pol=1) or falling edge triggered (if gp6_pol=0) 1 = gpio interrupt is triggered on rising and falling edges 11 gp6_pwr_do m 0 gpio6 power domain select 0 = dbvdd 1 = sysvdd 10 gp6_pol 1 gpio6 polarity select 0 = inverted (active low) 1 = non-inverted (active high) 9 gp6_od 0 gpio6 output pin configuration 0 = cmos 1 = open drain 8 gp6_ena 0 gpio6 enable control 0 = gpio pin is tri-stated 1 = normal operation 7:4 gp6_fn [3:0] 0000 gpio6 pin function input functions: 0 = gpio input (long de-bounce) 1 = gpio input 2 = power on/off request 3 = sleep/wake request
WM8310 pre-production w pp, may 2012, rev 3.1 276 register address bit label default description refer to 4 = sleep/wake request (long de-bounce) 5 = sleep request 6 = power on request 7 = watchdog reset input 8 = dvs1 input 9 = dvs2 input 10 = hw enable1 input 11 = hw enable2 input 12 = hw control1 input 13 = hw control2 input 14 = hw control1 input (long de-bounce) 15 = hw control2 input (long de-bounce) output functions: 0 = gpio output 1 = 32.768khz oscillator output 2 = on state 3 = sleep state 4 = power state change 5 = reserved 6 = reserved 7 = reserved 8 = dc-dc1 dvs done 9 = dc-dc2 dvs done 10 = external power enable1 11 = external power enable2 12 = system supply good (sysok) 13 = converter power good (pwr_good) 14 = external power clock (2mhz) 15 = auxiliary reset 3:1 sysok_thr [2:0] 101 sysok threshold (rising sysvdd) this is the rising sysvdd voltage at which sysok will be asserted 000 = 2.8v 001 = 2.9v ? 111 = 3.5v note that the sysok hysteresis margin is added to these threshold levels. register 781fh gpio6 otp control register address bit label default description refer to r30759 (7827h) ice check data 15:0 ice_valid_d ata [15:0] 0000_0000 _0000_000 0 this field is checked in development mode when an ?on? transition is requested. a value of a596h is required to confirm valid data. register 7827h ice check data
pre-production WM8310 w pp, may 2012, rev 3.1 277 30 applications information 30.1 typical connections WM8310 sclk2 sda2 2 wire i2c device id 34h sclk1 sda1 2 wire i2c slave sdout gpio12 gpio11 gpio10 gpio9 gpio8 gpio7 gpio6 gpio5 gpio4 gpio3 gpio2 gpio1 progvdd cpu_rtc ldo1vout ldo2vout ldo3vout ldo4vout ldo5vout ldo6vout ldo7vout ldo8vout ldo9vout ldo10vout ldo11vout mobile tv wifi hd radio rf cpu_io_block cpu_otg cpu_adc cpu_pll cpu alive cifmode / cs clkout clkin hd radio core 32khz in 12.288mhz mclk out cpu_dac configuration data loaded from internal otp irefr vrefc dc4fb dc4lx backlight led supply r1 r2 dc4gnd white led backlight ldo13vout ldo12vout isinkgnd dbgnd dc4vdd isink1 isink2 ldo1vdd ldo2vdd ldo3vdd ldo4vdd ldo5vdd ldo9vdd ldo10vdd ldo6vdd ldo7vdd ldo8vdd auxadcin1 auxadcin2 auxadcin3 auxadcin4 refgnd dcdc3vout sysvdd cc sink dcdc3vout gnd pvdd dbvdd dcdc3vdd dcdc2vdd dcdc1vdd / on / reset usb power in wallvdd dbvdd usbvdd singlecell li-ion battery sysvdd system power in battvdd / wallfetena battvmon usbvmon sysvmon / battfetena ntcmon ntcbias ntc external voltage measurement inputs general purpose input/output pins / irq 32khz xto xti xoscgnd charger on led2 power status led1 sysvdd memory nor / ddr_sdram cpu internal logic & caches cpu arm core dc1fb dc1lx dc1gnd dc2fb dc2lx dc2gnd dc3fb dc3lx dc3gnd backup battery figure 33 WM8310 typical connections diagram
WM8310 pre-production w pp, may 2012, rev 3.1 278 for detailed schematics, bill of materials and recommended external components refer to the WM8310 evaluation board users manual. 30.2 voltage and current reference components a decoupling capacitor is required between vr efc and refgnd; a 100nf x5r capacitor is recommended (available in 0201 package size). if usb100ma_startup=1x (see section 17.4), then a 50nf capacitor should be used. a current reference resistor is required between irefr and refgnd; a 100k ? (1%) resistor is recommended. 30.3 dc-dc buck converter external components the recommended connections to the dc-dc buck c onverters are illustrated in figure 34. figure 34 dc-dc synchronous buck converter external components when selecting suitable capacitors, is it imperativ e that the effective capacitance is within the required limits at the applicable input/output voltage of the converter. it should be noted that some components? capacitance changes significantly depending on the dc voltage applied. ceramic x7r or x5r types are recommended. the choice of output capacitor varies depending on the required transient re sponse. larger values may be required for optimum performance under large load transient conditions . smaller values may be sufficient for a steady load, or in applicati ons without stringent requirements on output voltage accuracy during load transients. for layout and size reasons, users may choose to implement large values of output capacitance by connecting two or more capacitors in para llel. to ensure stable operation, the dc m _cap register fields must be set according to the output capacitance, as described in section 15.6. when selecting a suitable output inductor, the i nductance value and the saturation current must be compatible with the operating conditions of the converter. the magnitude of the inductor current rippl e is dependant on the inductor value and can be determined by the following equation:
pre-production WM8310 w pp, may 2012, rev 3.1 279 as a minimum requirement, the dc current rating should be equal to the maximum load current plus one half of the inductor current ripple: to be suitable for the application, the chosen inducto r must have a saturation current that is higher than the peak inductor current given by the above equati on. to maximise the c onverter efficiency, the inductor should also have a low dc resistance (dcr), resulting in minimum conduction losses. care should also be taken to ensure that the component?s inductance is valid at the applicable operating temperature. the WM8310 incorporates a current-limit protection feature for all dc-dc buck converter outputs. in order to achieve the benefit of this feature, the out put inductor saturation current limit must be greater than or equal to the p-channel current limit for the applicable converter (see section 7). wolfson recommends the following external com ponents for use with dc-dc converters 1 and 2. the output inductor must be consistent with the dc m _freq register settings. the supported configurations are listed in table 107. note that for output voltages greater than 1.4v, the 2mhz mode must be used. dcm_freq switching frequency output inductor comments 00 n/a n/a n/a 01 2mhz 2.2 ? h best efficiency 10 n/a n/a n/a 11 4mhz 0.5 ? h best transient performance table 107 output inductor selection - dc-dc1, dc-dc2 the output capacitor must be consistent with the dc m _cap register settings. for best performance, the 47 ? f component is recommended. for typical applications, the 22 ? f is suitable. the alternative values may be used for size or cost reasons if preferred. component value part number size l 0.5? h coilcraft xpl2010-501mlb 2 x 2.5 x 1mm 2.2? h coilcraft lps3015-222ml tdk vls252012t-2r2m1r3 3 x 3 x 1.5mm 2 x 1.25 x 1.2mm c out 47? f murata grm21br60g476mea1 0805 22? f murata grm21br60j226me39 0805 10? f murata grm188r60j106me84 0603 4.7? f murata grm188r60j475me84 0603 c in 10? f murata grm188r60j106me84 0603 table 108 recommended external components - dc-dc1, dc-dc2
WM8310 pre-production w pp, may 2012, rev 3.1 280 wolfson recommends the following external components for use with dc-dc converter 3. note that the switching frequency of dc-dc3 is fi xed at 2mhz and the output inductor must be 2.2 ? h in all cases. the output capacitor must be consistent with t he dc3_cap register setting. for best performance, the 47 ? f component is recommended. for typical applications, the 22 ? f is suitable. the alternative values may be used for size or cost reasons if preferred. component value part number size l 2.2? h coilcraft lps3015-222ml tdk vls252012t-2r2m1r3 3 x 3 x 1.5mm 2 x 1.25 x 1.2mm c out 47? f murata grm21br60g476mea1 0805 22? f murata grm21br60j226me39 0805 10? f murata grm188r60j106me84 0603 c in 4.7? f murata grm188r60j475me84 0603 table 109 recommended external components - dc-dc3
pre-production WM8310 w pp, may 2012, rev 3.1 281 30.4 dc-dc (step-up) converter external components the recommended connections to the dc-dc (step-up ) converter are illustrated in figure 35. figure 35 dc-dc (step-up) converters external components in the constant current mode, the dc-dc conver ter output voltage is controlled by the WM8310 in order to achieve the required current in isink1 or isink2. the required current is set by the csn_isel register fields, as described in section 16.2.2. a typical application for this mode would be a white led driver, where several leds are connec ted in series to achieve uniform brightness. the dc-dc (step-up) converter is capable of generat ing output voltages of up to 30v. the maximum output voltage is determined by the two external resi stors r1 and r2, which form a resistive divider between load connection and the voltage feedback pin dc4fb. the maximum output voltage is set as described in the following equation: setting r2 to 47k ? is recommended for most applications; r1 can be calculated using the following equation, given the required output voltage: r1 = r2 . (2v out ?1) note that the resistors determine the maximum output voltage. the actual voltage will be determined by the selected isink current, subject to the device limits. when selecting a suitable capacitor, is it imperativ e that the effective capacitance is within the required limits at the applicable input/output voltage of the converter. ceramic x7r or x5r types are recommended. the choice of output capacitor for dc-dc4 varies depending on the required output voltage. see table 110 for further details.
WM8310 pre-production w pp, may 2012, rev 3.1 282 when selecting a suitable output inductor, the i nductance value and the saturation current must be compatible with the operating conditions of the converter. the magnitude of the inductor current rippl e is dependent on the inductor value and can be determined by the following equation: the inductor current is also a function of the dc-dc converter maximum input current, which can be determined by the following equation: as a minimum requirement, the dc current rating should be equal to the maximum input current plus one half of the inductor current ripple. to be suitable for the application, the chosen inducto r must have a saturation current that is higher than the peak inductor current given by the above equati on. to maximise the c onverter efficiency, the inductor should also have a low dc resistance (dcr), resulting in minimum conduction losses. care should also be taken to ensure that the com ponent?s inductance is suitable at the applicable operating temperature. wolfson recommends the following external components for use with dc-dc converter 4. the output capacitor c out must be selected according to the required output voltage. for 10v output, 4.7? f is recommended. for 15v output, 3.3 ? f is recommended. for 20-30v output, 1.5 ? f is recommended. the resistors r1 and r2 must be selected according to the required output voltage - refer to the equations above. the values quoted bel ow are suitable for 20v output. component value part number size l 10? h taiyo-yuden nr3015t100m 3 x 3 x 1.5mm c out 4.7? f murata grm31cr61c475ka01 1206 3.3? f murata grm31cr71c335ka01 1206 1.5? f murata grm31cr71h225ka88 1206 c in 2.2? f murata grm188r61a5ke34 0603 fet + shottky diode vishay sia814dj-t1-ge3 sc-70-6 2.05 x 2.05 x 0.75mm r1 1.8m ? phycomp 2322 7046 1805 0603 r2 47k ? multicomp mic 0.063w 0603 1% 47k 0603 table 110 recommended external components - dc-dc4
pre-production WM8310 w pp, may 2012, rev 3.1 283 30.5 ldo regulator external components the recommended connections to the ldo regulators are illustrated in figure 36. figure 36 ldo regulators external components when selecting suitable capacitors, is it imperativ e that the effective capacitance is within the required limits at the applicable input/output voltage of the converter. ceramic x7r or x5r types are recommended. wolfson recommends the following external components for use with ldo regulators 1 to 6. component value part number size c out 2.2 f kemet c0402c225m9pac 0402 c in 1.0 f murata grm155r61a105ke15 0402 table 111 recommended external components - ldo1 to ldo6 wolfson recommends the following external components for use with ldo regulators 7 to 10. for these regulators, note that it is important that the output capacitance, c out , does not exceed 4.7 ? f. component value part number size c out 1.0 f murata grm155r61a105ke15 0402 c in 1.0 f murata grm155r61a105ke15 0402 table 112 recommended external components - ldo7 to ldo10 wolfson recommends the following external components for use with ldo regulators 11 to 13. component value part number size c out (ldo11) 0.1 f murata grm033r60j104ke19 0201 c out (ldo12) 0.1 f murata grm033r60j104ke19 0201 c out (ldo13) 2.2 f kemet c0402c225m9pac 0402 table 113 recommended external components - ldo11 to ldo13
WM8310 pre-production w pp, may 2012, rev 3.1 284 30.6 battery temperature monitoring components battery temperature monitoring is performed using a reference voltage output on the ntcbias pin. a potential divider is formed between the ntc bias re sistor and the ntc thermistor component within the battery pack. the voltage present at the ntcmon pin is used to determine the battery temperature. the recommended connec tions and the derivation of v ntcmon is shown in figure 37. figure 37 battery temperature monitoring the voltage thresholds for the hot/cold battery temperature conditions are fixed in the WM8310: the cold battery condition is detected when v ntcmon > 0.765 x v ntcbias the hot battery condition is detected when v ntcmon < 0.348 x v ntcbias if the ntc thermistor has a nominal resistance of 100k ? at 25? c, and follows the vishay resistance- temperature curve 1, then the above equations result in the hot battery threshold = 40 ? c and the cold battery threshold = 0 ? c. for example, if the ntc thermistor resistance is 53.4k ? at 40 ? c, then v ntcmon is given by the following equation: the upper and lower temperature thresholds can be adjus ted by modification of the ntc bias resistor and/or the addition of another resistor between the battery pack and the ntcmon pin. if only the ntc bias resistor is adj usted, then either the upper or lower threshold can be selected, but not both; the other threshold will be determi ned by the thermistor characteristics. if an additional resistor is inserted between the battery pack and the ntcmon pin, then the upper and lower thresholds can be independently selected, with the constraint that the upper and lower thresholds must be at least 40 ? c apart.
pre-production WM8310 w pp, may 2012, rev 3.1 285 to select a specific hot battery threshold, the required ntc bias resistor value may be calculated using the following equation: r bias = (r hot / 0.534) x r 25 r hot is the ntc thermistor resistance rati o at the desired temperature threshold r 25 is the ntc thermistor resistance at 25 ? c for example, at 60 ? c the vishay curve 1 resistance ratio, r hot , is 0.2488. therefore, to implement a 60 ? c hot battery threshold, assuming a 100k ? ntc thermistor (at 25? c), the required ntc bias resistor is 46.6k ? (nearest e12 value 47k ? ). the resultant cold battery th reshold is given using the r cold equation below. the r cold value needs to be referenced to the vishay curve 1 resistance chart in order to find the corresponding temperature. to select a specific cold battery threshold, t he required ntc bias resistor value may be calculated using the following equation: r bias = (r cold / 3.255) x r 25 r cold is the ntc thermistor resistance rati o at the desired temperature threshold r 25 is the ntc thermistor resistance at 25 ? c for example, at 5 ? c the vishay curve 1 resistance ratio, r cold , is 2.540. therefore, to implement a 5 ? c cold battery threshold, assuming a 100k ? ntc thermistor (at 25? c), the required ntc bias resistor is 78k ? (nearest e12 value 82k ? ). the resultant hot battery thre shold is given using the r hot equation below. the r hot value needs to be referenced to the vishay curve 1 resistance chart in order to find the corresponding temperature. to select both the hot battery threshold and the cold battery threshold, an additional resistor, r1, is required, as illustrated in figure 38. ntc figure 38 battery temperature threshold selection
WM8310 pre-production w pp, may 2012, rev 3.1 286 under the circuit configuration above, the ntc bias resistors r bias and r 1 are calculated using the following equations: r bias = ((r cold - r hot ) / 2.721) x r 25 r 1 = (0.534 x r bias ) - (r hot x r 25 ) for example, to select a 45 ? c hot battery threshold and a 0 ? c cold battery threshold, the applicable resistance ratios are r hot = 0.4368 and r cold = 3.266. assuming a 100k ? ntc thermistor (at 25? c), then r 25 = 100k ? . from the equations above, it follows that r bias = 104k ? (nearest e12 value 100k ? ). assuming the e12 (100k ? ) value of r bias , then r 1 = 9.72k ? (nearest e12 value 10k ? ).
pre-production WM8310 w pp, may 2012, rev 3.1 287 30.7 pcb layout poor pcb layout will degrade the performance and be a contributory factor in emi, ground bounce and resistive voltage losses. poor regulation and instability can result. simple design rules can be implemented to negate these effects: external input and output capacitor s should be placed as close to the device as possible using short wide traces between the external power components. for the dc-dc converters, the input capacitor placement takes priority on the dc-dc converters. (for the ldo regulators, the placement of the input and output capacitors have equal priority.) route the dc-dc converter output voltage feedback as an independent connection to the top of the output capacitor to create a true sense of the output voltage, routing away from noisy signals such as the lx connection. use a local ground island for each i ndividual dc-dc converte r connected at a single point onto a fully flooded ground plane. current loop areas should be kept as small as possible with loop ar eas changing little during alternating switching cycles. studying the layout below shows, for example, dc-dc1 layout with external components c3, l3 and c6. the input capacitor, c6, is close into the ic and shares a small ground island with the output capacitor c3. the inductor, l3, is situated in clos e proximity to c3 in order to keep loop area small and minimise the trace resistance. note also the us e of short wide traces with all power tracking on a single (top) layer.
WM8310 pre-production w pp, may 2012, rev 3.1 288 31 package diagram dm062.c b: 169 ball bga plastic package 7 x 7 x 1.2 mm body, 0.50 mm ball pitch notes: 1. primary datum -z- and seating plane are defined by the spherical crowns of the solder balls. 2. this dimension includes stand-off height ?a1?. 3. dimension ?b? is measured at the maximum solder ball diameter, parallel to primary datum -z-. 4. a1 corner is identified by ink/laser mark on top package. 5. bilateral tolerance zone is applied to each side of the package body. 6. ?e? represents the basic solder ball grid pitch. 7. this drawing is subject to change without notice. 8. falls within jedec, mo-195 3 yz ccc x detail 1 solder ball b z ddd detail 2 a1 z aaa z bbb z 1 a1 corner top view e z 0.10 2 x d 5 4 detail 2 a a2 2 z 0.10 2 x detail 1 e bottom view 6 1 98765432 1011 1213 a d c b j h g f e k l m n e e1 d1 side view a1 0.21 0.11 b d d1 e e1 e 0.30 0.20 7.00 bsc 6.00 bsc 0.50 bsc 7.00 bsc 6.00 bsc dimensions (mm) symbols min nom max note a 1.20 a2 0.91 ref 0.20 aaa bbb ccc 0.08 0.15 tolerances of form and position ddd 0.08 6 ref: jedec, mo-195, variation ad
pre-production WM8310 w pp, may 2012, rev 3.1 289 32 important notice wolfson microelectronics plc (?wol fson?) products and services are sold subject to wolfson?s terms and conditions of sale, delivery and payment supplied at the time of order acknowledgement. wolfson warrants performance of its products to the specifications in effect at t he date of shipment. wolfson reserves the right to make changes to its products and s pecifications or to discontinue any product or service without notice. customers should therefore obtain the latest version of relevant information from wolfson to verify that the information is current. testing and other quality control techniques are utilised to the extent wolfson deems necessary to support its warranty. specific testing of all parameters of each device is not necessarily performed unless requi red by law or regulation. in order to minimise risks associated with customer app lications, the customer must use adequate design and operating safeguards to minimise inherent or procedur al hazards. wolfson is not liable for app lications assistance or customer product design. the customer is solely respons ible for its selection and use of wolfson products. wolfson is not liable for such selection or use nor for use of any circuitry other than circuitry entirely embodied in a wolfson product. wolfson?s products are not intended for use in life support systems, appliances, nuclear systems or systems where malfunction can reasonably be expected to resu lt in personal injury, death or severe property or environmental damage. any use of products by the customer for such pur poses is at the customer?s own risk. wolfson does not grant any licence (express or implied) under any patent right, copyright, mask work right or other intellectua l property right of wolfson covering or relating to any combination, machine, or process in which its products or services might be or are used. any provision or publication of any third party ?s products or services does not constitute wolfson?s approval, licence, warranty or endorsement thereof. any third party tr ade marks contained in this docum ent belong to the respective third party owner. reproduction of information from wolfson datasheets is per missible only if reproduction is without alteration and is accompanied by all associated copyright, proprietary and other not ices (including this notice) and conditions. wolfson is not liable for any unauthorised alteration of such info rmation or for any reliance placed thereon. any representations made, warranties giv en, and/or liabilities accepted by any pers on which differ from those contained in this datasheet or in wolfson?s standard terms and conditions of sale, delivery and payment are made, given and/or accepted at that person?s own risk. wolfson is not liable for any such representations, warranties or liabilities or for any reliance pl aced thereon by any person. address: wolfson microelectronics plc westfield house 26 westfield road edinburgh eh11 2qb united kingdom tel :: +44 (0)131 272 7000 fax :: +44 (0)131 272 7001 email :: sales@wolfsonmicro.com
WM8310 pre-production w pp, may 2012, rev 3.1 290 33 revision history date rev description of changes changed by 18/02/10 3.1 updated definition of dcn_soft_start registers rst_dur description updated updated description of aux_cvt_ena - measurement data is not available until the associated interrupt is set. auxadc input impedance corrected to 400kohm. ph 24/06/10 3.1 amended ldo12 current capability to 2ma. amended ldo13 current capability to 20ma dc4 maximum current spec restored to 90ma. dc4 elec chars updated to include 90ma for vload 8v. dc4_range updated to support vout >= 6.5v only. amended test conditions for ldo4, 5, 6 to be same as others. clarified (in section 13) the 32.768khz gpio output only supported in off state if the selected power domain remains on. clarified (in section 21) the external power clock is controlled in the power sequences via epe1 or epe2. updated wording and terminology, maki ng consistent with other pmic datasheets. review input from wm8321 incorporated as applicable. dorw replaced with dcrw. dbe replaced with instantconfig? eeprom (ice). added sdout1 pull-up requirement. typical connections drawing updated to s how xoscgnd close to xti/xto pins and to include dc-dc output capacitors. ph 22/07/10 3.1 noted maximum output capacitance for ldo7-ldo10 (4.7uf). updates regarding battery charger inte rrupts preventing sleep transitions - chg_start_eint must be cleared first. clarification added to clkout function when xtal_inh=1. correction to pin c5 - this is dc3gnd. dbvdd1, dbvdd2, dbvdd3 domains merged into dbvdd. pvdd1, pvdd2 domains merged into pvdd. watchdog description updated wrt device reset response. sdout1 description updated as an open drain output, with pull-up resistor required. ?register map by address? section updated. default value of pwrstate_dly corrected. ph 24/11/10 3.1 ce000609 errata added (otp command end interrupt) ce000610 errata added (dc3 quiescent current in ldo mode) ce000611 errata added (power sequenc e in failure conditions) ce000613 errata added (dc4 hardware control) ce000614 errata added (fll register readback) ce000649 errata added (watchdog timeout) ph 3/12/10 3.1 undervoltage margin specified for dc-dc converters 1,2,3. overvoltage margin specified for dc-dc converters 1,2. chip temperature (aux_data) equation updated. ntcbias voltage added to electrical characteristics. ph
pre-production WM8310 w pp, may 2012, rev 3.1 291 date rev description of changes changed by 07/03/11 3.1 rtc_pint_freq definition updated. added notes that sleep > off is not a controlled transiti on; converters and regulators are disabled immediately. reset pin description updated to note integrated pull-up. irq description updated to note pull-up in open drain mode. system reset and device reset descriptions updated, consistent with the summary table. recommended external pull-up resistances added in pin description. internal pull-up / pull-down resistances added in electrical characteristics. ce000612 errata added (gpn_pol in development mode) ph 28/03/11 3.1 noted maximum limit on software resets. also clarification of the maximum number of watchdog / undervoltage device resets. ce000607 errata added (device start-up, usb_ilim < 100ma). ce000608 errata added (power up failure, usb100ma_startup = 10 or 11). ph 28/06/11 3.1 dc-dc output inductor saturation limit recommendations added. sysok_thr register description updated. ph 21/09/11 3.1 backup battery power updated; backup charger control registers deleted. ldo11 output amended for ldo11_vsel_src=1 and dc-dc1 disabled. ph 17/04/12 3.1 order codes changed from WM8310geb/v and WM8310geb/rv to WM8310 c geb/v and WM8310 c geb/rv to reflect change to copper wire bonding. jmacd 17/04/12 3.1 package diagram updated to dm062c to re flect change to copper wire bonding. jmacd 02/05/12 3.1 electrical characteristics updated ldo7, 8, 9, 10 input voltage range updated. ldo11 current rating updated. ph

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